Datasheet
ADC08200
www.ti.com
SNAS136M –APRIL 2001–REVISED MARCH 2013
Converter Electrical Characteristics
The following specifications apply for V
A
= V
DR
= +3.0V
DC
, V
RT
= +1.9V, V
RB
= 0.3V, C
L
= 5 pF, f
CLK
= 200 MHz at 50% duty
cycle. Boldface limits apply for T
J
= T
MIN
to T
MAX
: all other limits T
J
= 25°C
(1)(2)(3)
Units
Symbol Parameter Conditions Typical
(4)
Limits
(4)
(Limits)
DC ACCURACY
+1.0 +1.9 LSB (max)
INL Integral Non-Linearity
−0.3 −1.2 LSB (min)
DNL Differential Non-Linearity ±0.4 ±0.95 LSB (max)
Missing Codes 0 (max)
FSE Full Scale Error 36 50 mV (max)
V
OFF
Zero Scale Offset Error 46 60 mV (max)
ANALOG INPUT AND REFERENCE CHARACTERISTICS
V
RB
V (min)
V
IN
Input Voltage 1.6
V
RT
V (max)
(CLK LOW) 3 pF
C
IN
V
IN
Input Capacitance V
IN
= 0.75V +0.5 Vrms
(CLK HIGH) 4 pF
R
IN
R
IN
Input Resistance >1 MΩ
BW Full Power Bandwidth 500 MHz
V
A
V (max)
V
RT
Top Reference Voltage 1.9
0.5 V (min)
V
RT
− 0.5 V (max)
V
RB
Bottom Reference Voltage 0.3
0 V (min)
1.0 V (min)
V
RT
- V
RB
Reference Voltage Delta 1.6
2.3 V (max)
120 Ω (min)
R
REF
Reference Ladder Resistance V
RT
to V
RB
160
200 Ω (max)
CLK, PD DIGITAL INPUT CHARACTERISTICS
V
IH
Logical High Input Voltage V
DR
= V
A
= 3.6V 2.0 V (min)
V
IL
Logical Low Input Voltage V
DR
= V
A
= 2.7V 0.8 V (max)
I
IH
Logical High Input Current V
IH
= V
DR
= V
A
= 3.6V 10 nA
I
IL
Logical Low Input Current V
IL
= 0V, V
DR
= V
A
= 2.7V −50 nA
C
IN
Logic Input Capacitance 3 pF
(1) The Electrical characteristics tables list ensured specifications under the listed Recommended Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations for room temperature only
and are not ensured.
(2) The analog inputs are protected as shown below. Input voltage magnitudes up to V
A
+ 300 mV or to 300 mV below GND will not
damage this device. However, errors in the A/D conversion can occur if the input goes above V
DR
or below GND by more than 100 mV.
For example, if V
A
is 2.7V
DC
the full-scale input voltage must be ≤2.8V
DC
to ensure accurate conversions.
(3) To ensure accuracy, it is required that V
A
and V
DR
be well bypassed. Each supply pin must be decoupled with separate bypass
capacitors.
(4) Typical figures are at T
J
= 25°C, and represent most likely parametric norms. Test limits are specifid to TI's AOQL (Average Outgoing
Quality Level).
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