Datasheet

V
D
DGND
ADC08200
www.ti.com SNAS136M –APRIL 2001–REVISED MARCH 2013
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
Pin No. Symbol Equivalent Circuit Description
6 V
IN
Analog signal input. Conversion range is V
RB
to V
RT
.
Analog Input that is the high (top) side of the reference ladder
of the ADC. Nominal range is 0.5V to V
A
. Voltage on V
RT
and
3 V
RT
V
RB
inputs define the V
IN
conversion range. Bypass well. See
THE ANALOG INPUT for more information.
Mid-point of the reference ladder. This pin should be bypassed
9 V
RM
to a quiet point in the ground plane with a 0.1 µF capacitor.
Analog Input that is the low side (bottom) of the reference
ladder of the ADC. Nominal range is 0.0V to (V
RT
– 0.5V).
10 V
RB
Voltage on V
RT
and V
RB
inputs define the V
IN
conversion
range. Bypass well. See THE ANALOG INPUT for more
information.
Power Down input. When this pin is high, the converter is in
23 PD the Power Down mode and the data output pins hold the last
conversion result.
CMOS/TTL compatible digital clock Input. V
IN
is sampled on
24 CLK
the rising edge of CLK input.
13 thru 16 Conversion data digital Output pins. D0 is the LSB, D7 is the
and D0–D7 MSB. Valid data is output just after the rising edge of the CLK
19 thru 22 input.
7 V
IN
GND Reference ground for the single-ended analog input, V
IN
.
Positive analog supply pin. Connect to a quiet voltage source
of +3V. V
A
should be bypassed with a 0.1 µF ceramic chip
1, 4, 12 V
A
capacitor for each pin, plus one 10 µF capacitor. See POWER
SUPPLY CONSIDERATIONS for more information.
Power supply for the output drivers. If connected to V
A
,
18 V
DR
decouple well from V
A
.
17 DR GND The ground return for the output driver supply.
2, 5, 8, 11 AGND The ground return for the analog supply.
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