Datasheet

I
OL
200 PA
I
OH
200 PA
1.6 V
To Output Pin
C
L
25 pF
ADC081S101
SNAS310C –JANUARY 2006–REVISED MARCH 2013 www.ti.com
ADC081S101 Timing Specifications
The following specifications apply for V
A
= +2.7V to 5.25V, GND = 0V, f
SCLK
= 10.0 MHz to 20.0 MHz, C
L
= 25 pF, f
SAMPLE
=
500 ksps to 1 Msps, Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Symbol Parameter Conditions Typical Limits Units
t
CS
Minimum CS Pulse Width 10 ns (min)
t
SU
CS to SCLK Setup Time 10 ns (min)
t
EN
Delay from CS Until SDATA TRI-STATE Disabled
(1)
20 ns (max)
V
A
= +2.7 to +3.6 40 ns (max)
t
ACC
Data Access Time after SCLK Falling Edge
(2)
V
A
= +4.75 to +5.25 20 ns (max)
t
CL
SCLK Low Pulse Width 0.4 x t
SCLK
ns (min)
t
CH
SCLK High Pulse Width 0.4 x t
SCLK
ns (min)
V
A
= +2.7 to +3.6 7 ns (min)
t
H
SCLK to Data Valid Hold Time
V
A
= +4.75 to +5.25 5 ns (min)
25 ns (max)
V
A
= +2.7 to +3.6
6 ns (min)
t
DIS
SCLK Falling Edge to SDATA High Impedance
(3)
25 ns (max)
V
A
= +4.75 to +5.25
5 ns (min)
t
POWER-
Power-Up Time from Full Power-Down 1 µs
UP
(1) Measured with the timing test circuit shown in Figure 2 and defined as the time taken by the output signal to cross 1.0V.
(2) Measured with the timing test circuit shown in Figure 2 and defined as the time taken by the output signal to cross 1.0V or 2.0V.
(3) t
DIS
is derived from the time taken by the outputs to change by 0.5V with the timing test circuit shown in Figure 2. The measured number
is then adjusted to remove the effects of charging or discharging the output capacitance. This means that t
DIS
is the true bus relinquish
time, independent of the bus loading.
Timing Diagrams
Figure 2. Timing Test Circuit
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