Datasheet

ADC081S051
SNAS309E –APRIL 2005–REVISED MARCH 2013 www.ti.com
USING THE ADC081S051
The serial interface timing diagram for the ADC is shown in Figure 3. CS is chip select, which initiates
conversions on the ADC and frames the serial data transfers. SCLK (serial clock) controls both the conversion
process and the timing of serial data. SDATA is the serial data out pin, where a conversion result is found as a
serial data stream.
Basic operation of the ADC begins with CS going low, which initiates a conversion process and data transfer.
Subsequent rising and falling edges of SCLK will be labelled with reference to the falling edge of CS; for
example, "the third falling edge of SCLK" shall refer to the third falling edge of SCLK after CS goes low.
At the fall of CS, the SDATA pin comes out of TRI-STATE and the converter moves from track mode to hold
mode. The input signal is sampled and held for conversion on the falling edge of CS. The converter moves from
hold mode to track mode on the 13th rising edge of SCLK (see Figure 3). It is at this point that the interval for the
T
ACQ
specification begins. In the worst case, 350ns must pass between the 13th rising edge and the next falling
edge of SCLK. The SDATA pin will be placed back into TRI-STATE after the 16th falling edge of SCLK, or at the
rising edge of CS, whichever occurs first. After a conversion is completed, the quiet time (t
QUIET
) must be
satisfied before bringing CS low again to begin another conversion.
Sixteen SCLK cycles are required to read a complete sample from the ADC. The sample bits (including leading
or trailing zeroes) are clocked out on falling edges of SCLK, and are intended to be clocked in by a receiver on
subsequent rising edges of SCLK. The ADC will produce three leading zero bits on SDATA, followed by eight
data bits, most significant first. After the data bits, the ADC will clock out four trailing zeros.
If CS goes low before the rising edge of SCLK, an additional (fourth) zero bit may be captured by the next falling
edge of SCLK.
Determining Throughput
Throughput depends on the frequency of SCLK and how much time is allowed to elapse between the end of one
conversion and the start of another. At the maximum specified SCLK frequency, the maximum specified
throughput is obtained by using a 20 SCLK frame. As shown in Figure 3, the minimum allowed time between CS
falling edges is determined by 1) 12.5 SCLKs for Hold mode, 2) the larger of two quantities: either the minimum
required time for Track mode (t
ACQ
) or 2.5 SCLKs to finish reading the result and 3) 0, 1/2 or 1 SCLK padding to
ensure an even number of SCLK cycles so there is a falling SCLK edge when CS next falls. For example, at the
fastest rate for this family of parts, SCLK is 20MHz and 2.5 SCLKs are 125ns, so the minimum time between CS
falling edges is calculated by
12.5*50ns + 350ns + 0.5*50ns = 1000ns (2)
(12.5 SCLKs + t
ACQ
+ 1/2 SCLK) which corresponds to a maximum throughput of 1MSPS. At the slowest rate for
this family, SCLK is 1MHz. Using a 20 cycle conversion frame as shown in Figure 3 yields a 20μs time between
CS falling edges for a throughput of 50KSPS. It is possible, however, to use fewer than 20 clock cycles provided
the timing parameters are met. With a 1MHz SCLK, there are 2500ns in 2.5 SCLK cycles, which is greater than
t
ACQ
. After the last data bit has come out, the clock will need one full cycle to return to a falling edge. Thus the
total time between falling edges of CS is 12.5*1μs +2.5*1μs +1*1μs=16μs which is a throughput of 62.5KSPS.
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