Datasheet

GND
SAMPLING
CAPACITOR
SW1
-
+
CONTROL
LOGIC
CHARGE
REDISTRIBUTION
DAC
SW2
V
IN
V
A
2
GND
SAMPLING
CAPACITOR
SW1
-
+
CONTROL
LOGIC
CHARGE
REDISTRIBUTION
DAC
SW2
V
IN
V
A
2
ADC081S051
www.ti.com SNAS309E –APRIL 2005–REVISED MARCH 2013
APPLICATIONS INFORMATION
ADC081S051 OPERATION
The ADC081S051 is a successive-approximation analog-to-digital converter designed around a charge-
redistribution digital-to-analog converter core. Simplified schematics of the ADC081S051 in both track and hold
modes are shown in Figure 18 and Figure 19, respectively. In Figure 18, the device is in track mode: switch SW1
connects the sampling capacitor to the input and SW2 balances the comparator inputs. The device is in this state
until CS is brought low, at which point the device moves to hold mode.
Figure 19 shows the device in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining
the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-
redistribution DAC to add or subtract fixed amounts of charge from the sampling capacitor until the comparator is
balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of
the analog input voltage. The device moves from hold mode to track mode on the 13th rising edge of SCLK.
Figure 18. ADC081S051 in Track Mode
Figure 19. ADC081S051 in Hold Mode
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