Datasheet

ADC08100
www.ti.com SNAS060I –JUNE 2000–REVISED MAY 2013
Converter Electrical Characteristics (continued)
The following specifications apply for V
A
= DR V
D
= +3.0V
DC
, V
RT
= +1.9V, V
RB
= 0.3V, C
L
= 10 pF, f
CLK
= 100 MHz at 50%
duty cycle. Boldface limits apply for T
J
= T
MIN
to T
MAX
: all other limits T
J
= 25°C
(1)(2)(3)
Typical Limits Units
Symbol Parameter Conditions
(4) (4)
(Limits)
POWER SUPPLY CHARACTERISTICS
DC Input 41 50 mA (max)
I
A
Analog Supply Current
f
IN
= 10 MHz, V
IN
= −3 dBFS 41 mA (max)
DC Input 1 2 mA (max)
DR I
D
Output Driver Supply Current
(5)
f
IN
= 10 MHz, V
IN
= −3 dBFS 8 mA (max)
DC Input 42 52
I
A
+
Total Operating Current f
IN
= 10 MHz, V
IN
= −3 dBFS, PD = Low 49 mA (max)
DR I
D
CLK Low, PD = Hi 0.2
DC Input 126 156 mW (max)
PC Power Consumption f
IN
= 10 MHz, V
IN
= −3 dBFS, PD = Low 147 mW
CLK Low, PD = Hi 0.6 mW
PSRR
1
Power Supply Rejection Ratio FSE change with 2.7V to 3.3V change in V
A
54 dB
Rejection of 150 mV at 9.8 MHz riding upon
PSRR
2
Power Supply Rejection Ratio 33 dB
supply
AC ELECTRICAL CHARACTERISTICS
f
C1
Maximum Conversion Rate 125 100 MHz (min)
f
C2
Minimum Conversion Rate 20 MHz
t
CL
Minimum Clock Low Time 4.5 ns (min)
t
CH
Minimum Clock High Time 4.5 ns (min)
t
OH
Output Hold Time CLK Rise to Data Invalid 4.4 ns
t
OD
Output Delay CLK Rise to Data Valid 5.9 8.5 ns (max)
Pipeline Delay (Latency) 2.5 Clock Cycles
t
AD
Sampling (Aperture) Delay CLK Fall to Acquisition of Data 1.5 ns
t
AJ
Aperture Jitter 2 ps rms
(5) I
DR
is the current consumed by the switching of the output drivers and is primarily determined by the load capacitance on the output
pins, the supply voltage, V
DR
, and the rate at which the outputs are switching (which is signal dependent), I
DR
= V
DR
(C
O
x f
O
+ C
1
x f
1
+ … + C
71
x f
7
) where V
DR
is the output driver power supply voltage, C
n
is the total capacitance on any given output pin, and f
n
is the
average frequency at which that pin is toggling.
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