Datasheet

V
D
DGND
V
RT
V
RM
256
1
SWITCHES
CLOCK
GEN
COARSE/FINE
COMPARATORS
ENCODER
& ERROR
CORRECTION
17
CLK
17
COARSE/FINE
COMPARATORS
ENCODER
& ERROR
CORRECTION
17
V
A
(pin 18)
AGND
V
IN
8
8
OUTPUT
DRIVERS
MUX
8 8
DATA
OUT
PD
DR V
D
DR GND
(pin 17)
V
RB
V
IN
GND
ADC08100
SNAS060I –JUNE 2000–REVISED MAY 2013 www.ti.com
Block Diagram
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
Pin No. Symbol Equivalent Circuit Description
6 V
IN
Analog signal input. Conversion range is V
RB
to V
RT
.
Analog Input that is the high (top) side of the reference ladder
of the ADC. Nominal range is 1.0V to V
A
. Voltage on V
RT
and
3 V
RT
V
RB
inputs define the V
IN
conversion range. Bypass well. See
THE ANALOG INPUT for more information.
Mid-point of the reference ladder. This pin should be bypassed
9 V
RM
to a clean, quiet point in the analog ground plane with a 0.1
µF capacitor.
Analog Input that is the low side (bottom) of the reference
ladder of the ADC. Nominal range is 0.0V to (V
RT
– 1.0V).
10 V
RB
Voltage on V
RT
and V
RB
inputs define the V
IN
conversion
range. Bypass well. See THE ANALOG INPUT for more
information.
Power Down input. When this pin is high, the converter is in
23 PD the Power Down mode and the data output pins hold the last
conversion result.
CMOS/TTL compatible digital clock Input. V
IN
is sampled on
24 CLK
the falling edge of CLK input.
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