Datasheet
22
+
-
200
12
240
47
100
10 pF
Signal
Input
8 11
AGND
ADC08100
D7
13
D6
14
D5
15
D0
22
D1
21
D2
20
D3
19
D4
16
6
3
7
10
V
RT
5
0.1 PF
10 PF
+
+
124 18
0.1 PF
10 PF
DR V
D
V
A
Choke
1
V
RB
24
CLK
9
23
PD
+3V
LMH6702
2
17
DR GND
+5V
-5V
0
.
1
P
F
0
.
1
P
F
10
Gain
Adjust
4.7k
1k1k
0
.
33
P
F
+3V
*
*
Offset Adjust
*
Ground connections marked
with "*" should enter the ground
plane at a common point.
V
IN
7
V
IN
GND
V
RM
ADC08100
www.ti.com
SNAS060I –JUNE 2000–REVISED MAY 2013
THE ANALOG INPUT
The analog input of the ADC08100 is a switch followed by an integrator. The input capacitance changes with the
clock level, appearing as 3 pF when the clock is low, and 4 pF when the clock is high. The sampling nature of
the analog input causes current spikes at the input that result in voltage spikes there. Any amplifier used to drive
the analog input must be able to settle within the clock high time. The LMH6702 and the LMH6628 have been
found to be good amplifiers to drive the ADC08100.
Figure 32 shows an example of an input circuit using the LMH6702. Any input amplifier should incorporate some
gain as operational amplifiers exhibit better phase margin and transient response with gains above 2 or 3 than
with unity gain. If an overall gain of less than 3 is required, attenuate the input and operate the amplifier at a
higher gain, as shown in Figure 32.
Figure 32. The Input Amplifier Should Incorporate Some Gain for Best Performance (see text)
The RC at the amplifier output filters the clock rate energy that comes out of the analog input due to the input
sampling circuit. The optimum time constant for this circuit depends not only upon the amplifier and ADC, but
also on the circuit layout and board material. A resistor value should be chosen between 18Ω and 47Ω and the
capacitor value chose according to the formula:
(4)
The value of "C" in the formula above should include the ADC input capacitance when the clock is high.
This will provide optimum SNR performance for Nyquist applications. Best THD performance is realized when the
capacitor and resistor values are both zero, but this would compromise SNR and SINAD performance. Generally,
there should be no resistor or capacitor between the ADC input and any amplifier for undersampling applications.
The circuit of Figure 32 has both gain and offset adjustments. If you eliminate these adjustments normal circuit
tolerances may cause signal clipping unless care is exercised in the worst case analysis of component tolerance
and the input signal excursion is appropriately limited to account for the worst case conditions. Of course, this
means that the designer will not be able to depend upon getting a full scale output with maximum signal input.
Full scale and offset adjustments may also be made by adjusting V
RT
and V
RB
, perhaps with the aid of a pair of
DACs.
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