Datasheet
22
+
-
200
12
240
47
100
10 pF
Signal
Input
8 11
AGND
ADC08060
D7
13
D6
14
D5
15
D0
22
D1
21
D2
20
D3
19
D4
16
6
3
7
10
V
RT
5
0.1 PF
10 PF
+
+
124 18
0.1 PF
10 PF
DR V
D
V
A
Choke
1
V
RB
24
CLK
9
23
PD
+3V
LMH6702
2
17
DR GND
+5V
-5V
0
.
1
P
F
0
.
1
P
F
10
Gain
Adjust
4.7k
1k1k
0
.
33
P
F
+3V
*
*
Offset
Adjust
*
*URXQGFRQQHFWLRQVPDUNHGZLWK³*´
should enter the ground plane at a
common point
V
IN
7
V
IN
GND
V
RM
ADC08060
SNAS120H –OCTOBER 2000–REVISED MARCH 2013
www.ti.com
The input amplifier should incorporate some gain for best performance (see text).
Figure 32.
The RC at the amplifier output filters the clock rate energy that comes out of the analog input due to the input
sampling circuit. The optimum time constant for this circuit depends not only upon the amplifier and ADC, but
also on the circuit layout and board material. A resistor value should be chosen between 18Ω and 47Ω and the
capacitor value chose according to the formula
(5)
This will provide optimum SNR performance. Best THD performance is realized when the capacitor and resistor
values are both zero. To optimize SINAD, reduce the capacitor or resistor value until SINAD performance is
optimized. That is, until SNR = −THD. This value will usually be in the range of 40% to 65% of the value
calculated with the above formula. An accurate calculation is not possible because of the board material and
layout dependence.
The above is intended for oversampling or Nyquist applications. There should be no resistor or capacitor
between the ADC input and any amplifier for undersampling applications.
The circuit of Figure 32 has both gain and offset adjustments. If you eliminate these adjustments normal circuit
tolerances may cause signal clipping unless care is exercised in the worst case analysis of component
tolerances and the input signal excursion is appropriately limited to account for the worst case conditions. Of
course, this means that the designer will not be able to depend upon getting a full scale output with maximum
signal input.
POWER SUPPLY CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt their own power supplies if not adequately bypassed. A
10 µF tantalum or aluminum electrolytic capacitor should be placed within an inch (2.5 cm) of the A/D power
pins, with a 0.1 µF ceramic chip capacitor placed within one centimeter of the converter's power supply pins.
Leadless chip capacitors are preferred because they have low lead inductance.
18 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: ADC08060