Datasheet
SNAU133 Page25
2.8 System Description
2.8.1 The ADC0XD1520
The ADC0XD1520 forms the heart of this reference board. This low-power, high-performance CMOS analog-to-
digital converter digitizes signals at 7/8-bit resolution at guaranteed minimum sampling rates of 1.5 Gs/s in dual
channel configuration and 3.0 Gs/s in single channel configuration. The ADC0XD1520 is targeted at achieving
very good accuracy and dynamic performance while consuming the lowest power available in the industry when
both channels are powered-up. Refer to the latest version of the ADC0XD1520 datasheet for more detailed
information.
This reference board gives complete control over the ADC0XD1520 and gives the user direct performance results of
the chip without the need for an elaborate setup. Each of the device's control pins may be set high or low. Control is
provided in two different manners - direct pin control with jumpers or through the serial interface (the device's extended
control mode) using the WV 5 register control panel. In order to use the extended control mode the ECE jumper must
be set to LOW. This is the recommended method and gives the user the most flexibility and ease of use.
Analog Front-End: The analog signal connection to the ADC is kept simple on this board in order to achieve the
highest possible bandwidth. The board is designed to be coupled to front-end circuitry in a DC or AC coupled manner.
AC-coupling requires the use of dc-blocks on the SMA connectors. By default, the board is shipped by TI with dc-
blocks. In addition, the board is also jumper-configured for DC-coupled operation (pin 9 on J15 is removed for DC
operation).
2.8.2 LMX2541 Clock Synthesis chip
The LMX2541xxxx family provides a single-chip, very low-jitter clock solution at frequencies up to 4.0 GHz. In
this application, the LMX2541SQ3030E is used - which can be programmed to operate over a range of 2810-
3230MHz. This output frequency from the VCO is divided to achieve the desired clocking frequency of the ADC.
On the ADC0XD1520RB board, the device is configured for a 1.5 GHz output through the serial interface. The
initial command sequence that automatically configures the LMX2541 is pre-programmed into the FPGA’s
firmware.
The clock source for the ADC can be selected between the on-board LMX2541 or an external clock source
connected through the J11 SMA connector. The selection is performed through the WV 5 register panel. It is
recommended that the external clock source should be connected and enabled before it is selected. For optimum
performance, the external clock signal generator and the LMX2541 should not be enabled at the same time. This
is because the RF relay used to select between them does not provide adequate isolation to keep one from affecting
the other. Having both clocks on simultaneously will result in excessive spurious signals. The default setting for
this board is the on-board LMX2541 clock source.
2.8.3 FPGA
The design employs a Xilinx Virtex-4 FPGA for capturing the digital data. While the board is powered up and
configured, the FPGA is continually receiving data from the ADC. In response to a user command through the WV-
5 software, the ADC captures the desired amount of data in its on-chip buffer (up to a maximum of 32K samples
per-channel). The user can then command the FPGA to upload the captured data to the PC through the USB
interface for further processing.