ADC0XD1520RB Reference Board Users’ Guide SNAU133 Page 1
Table of Contents 1.0 Overview 1.1 Features 1.2 Packing List 1.3 References 2.0 Quick Start 2.1 Installing the WaveVision 5 Software 2.2 Installing the ADC0XD1520RB Hardware 2.3 Launching the WaveVision 5 Software 2.4 WaveVision 5 – User Interface Overview 2.5 System / Device Configuration 2.6 Data Capturing 3.0 Secondary Panel Description 4.0 Reference Board Functional Description 4.1 System Block Diagram 4.2 System Description 5.
1.0 Overview The ADC0XD1520RB demonstrates a high-performance signal acquisition sub-system that achieves 7/8-bit resolution and corresponding SNR and dynamic range on two channels with sampling rates of at least 1.5 GS/s or one channel at a sampling rate of 3.0 GHz.
1.1 Features Demonstrates the ADC0XD1520's typical dynamic performance – see the datasheet for full details. Dual channel sample rates of up to 1.5 GS/s (limited by the ADC specifications and the FPGA capture limitations) Single channel (Interleaved) sample rates of up to 3.
1.4 Board Orientation Q-ch. Sig. I-ch. Sig. Ext Clock DCLK_RST Ext.
2.0 Quick Start This section will aid in bringing up the board for the first time as well as a brief tutorial on the WaveVision 5 (WV5) software. Further description of the Reference Board is in subsequent sections of this document. The software is further described in the WaveVision 5 Users' Guide or the HELP function within the software. The ADC0XD1520 and LMX2541 datasheets should be consulted for detailed understanding of device functionality.
2.1 Installing the WaveVision 5 Software 1. 2. 3. 4. Insert the included WaveVision 5 CD-ROM into the computer CD drive. Locate, unzip and run the install.bat program on the CD-ROM. Follow the on-screen instructions to complete the installation. Follow the WaveVision 5 Software Driver Installation Guide from www.ti.com/tool/wavevision5 to install the required drivers for the ADC board. This typically involves manually installing them from the “driver” folder in the WaveVision 5 directory. 2.
2.3 Launch the WaveVision 5 Software. Start the WaveVision 5 software on your computer by selecting the desktop icon “WaveVision 5” or by clicking on the Start button, and selecting Start -> Programs -> WaveVision 5 -> WaveVision 5 The software will automatically detect the board and load the appropriate software profile and will proceed to download the controller firmware and FPGA code onto the reference board. As an alternative, the icon on the desktop can be used to launch WaveVision 5.
2.4 WaveVision 5 - User Interface Overview Figure 3: WaveVision 5 Example Window Figure 3 above shows the WV5 user interface panel (GUI). This is the top level interface panel. It is arranged in such a way that the plot is always in the middle. There are tabs arranged on each side of the window to give the user additional information or control of features.
2.5 System / Device Configuration Prior to capturing data, confirm that the board is in the "ECE (Extended Control Enable)" mode, The ECE jumper is located in the ADC pin control jumper area. The board should be sent with this jumper in place. This means that the ADC will be controlled through the SPI interface and not with jumpers driving the control pins. This allows the user to control the ADC's behavior through the WaveVision 5 Registers panel.
2.5.1 Main Panel The main menu bar of the WaveVision 5 software has several control buttons as shown in Figures 4 and 5, which may be used to perform most tasks with a button click. 1 - Load Plot A new plot window is created and the Plot Load dialog is displayed. The selected plot file is loaded into the new window. 2 - Import Data Clicking this button creates a new time-domain plot and opens the Import Data dialog.
2.5.2 Plot Window Controls Figure 6: WaveVision 5 plot window controls 1 - Load Plot The Plot Load dialog is displayed, and the selected plot file is loaded into the new window. 2 - Save Plot Displays the Plot Save dialog (this button is only active when the plot contains one or more channels with data). 3 - Reset Zoom Reset X and Y axis zoom to 100%. 4 - Clear Clear data from all channels. 5 - Print Print the plot. 6 - Time Domain Display the plot as time domain data.
2.5.3 Right Panels – Signal Source Figure 7a: WaveVision 5 main window command buttons Open the Signal Source panel on the right side of the window and confirm that the ADC0XD1520RB is available and confirm that it is selected.
Note – When using “I and Q” mode, it is also necessary to select the Channels tab and deselect the “Automatically hide inactive channels” option box in order to allow both channels to appear on the plot.
Figure 8: WaveVision 5 main window command buttons • • • • • Sampling Rate - When the signal source panel is selected, the clock frequency is displayed. This is initially the internal clock. In this example, 1500 MHz is generated by the LMX2541 on the reference board. The sampling rate is determined by the FPGA when the board is powered up. The calculation is accurate to better than 1%. If an external source is in use, confirm that this number corresponds to the clock reference that is applied.
2.5.4 Right Panels - Registers Next, configure the hardware (including the ADC) using the Registers control panel on the right side. This is the most important of all the panels for controlling the ADC0XD1520RB. This panel has seven sub-tabs that control the settings of the board and registers inside the ADC0XD1520. The seven sub-tabs are shown below and include; Settings, Config, Extended Config, I-channel, Q-channel, tAD Adjust, and Temperature.
Config: This tab configures various features and modes of the ADC0XD1520 and is shown below. It accesses or changes the following functions, all of which are controlled through Configuration Register 1. Figure 10: Config Panel • • • • • • nSD – Second DCLK output – When this bit is 1b, the device only has one DCLK output and one OR output. When this output is 0b, the device has two identical DCLK outputs and no OR output.
Extended Config: This tab controls the extended configuration register. Figure 11: Extended Config Panel • • • TPO – Test Pattern Output – When this bit is set to 1b, the ADC is disengaged and a test pattern generator is connected to the outputs including OR. This test pattern will work with the device in the SDR, DDR, and the Non-demux Modes (DES and Non-DES).
I-channel: This tab changes the sign and the magnitude of the offset and the full scale range settings. Figure 12: I-Channel Panel • • • I-channel Offset Sign – This pull-down selects a positive or negative offset. I-ch Offset – This slider selects the magnitude of I-ch Offset applied. Adjustment can be done using the computer mouse/pointer, or using left/right arrow keys once the slider has been selected.
Phase Adjust: This tab controls the Aperture Delay function. Figure 13: tAD Adjust Panel • POL – Polarity Select – When this bit is selected, the polarity of the ADC sampling clock is inverted • Coarse Phase Adjust – Sets the approximate amount of coarse Aperture Delay applied. • • IPA – Intermediate Phase Adjust – Each code value in this field delays the sample clock by approximately 11 ps. A value of 000b in this field causes zero adjustment.
Figure 14: Temperature Panel • • • Ambient Temperature – Provides the local/board temperature of the LM95233 IC. ADC Temperature – Provides the approximate die temperature of the ADC0XD1520. FPGA Temperature – Provides the approximate die temperature of the Xilinx Virtex-4 FPGA. Note: No changes will appear until the Update Temperatures button is clicked.
2.6 Data Capturing The board is now ready for a data capture. Before proceeding, perform a manual calibration of the ADC. Even though the ADC performs a self-calibration at the time of power-up, it is recommended that the user perform another calibration after sufficient time has passed for the system (primarily temperature) to stabilize. Manual calibration is performed by clicking the Calibrate ADC feature in the Register control panel, Settings sub-tab. 2.6.
If the internal/external clock selection is changed, then the ADC should be re-calibrated. The required clock amplitude to the ADC may be found in the datasheet as VIN_CLK. For the ADC0XD1520, this range is {0.4Vpp, 2.0Vpp}. However, there is a significant insertion for the Teledyne relay, RF303, and other components on the ADC0XD1520RB, as shown in Figure 15. To compensate for this insertion loss, use the recommended values in Table 1.
Reference Board Functional Description 2.7 System Block Diagram 12V Power Management Analog_3.3/5.0V (for off-board use) Analog_3.3V Digital_3.3V Digital_2.5V Digital_1.8V Analog_1.9V Digital_1.2V Temp Sensor (LM95233) Analog Front-End Boards Plug-in Here (LMH6518, Balun, RF) 2 VinI +/ADC0xD1520 Vcmo DCLK_RST+/Ext Clock Clk Gen (LMX2541) Trigger SE2DIFF EEPROM I2C Vreg ORI/Q 7 or 8x2 2 DCLKI/Q +3.3V ADR/DATA 7 or 8x2 VinQ +/- Power Sequencing Control Xilinx Virtex-4 FPGA USB Ctrlr.
2.8 System Description 2.8.1 The ADC0XD1520 The ADC0XD1520 forms the heart of this reference board. This low-power, high-performance CMOS analog-todigital converter digitizes signals at 7/8-bit resolution at guaranteed minimum sampling rates of 1.5 Gs/s in dual channel configuration and 3.0 Gs/s in single channel configuration. The ADC0XD1520 is targeted at achieving very good accuracy and dynamic performance while consuming the lowest power available in the industry when both channels are powered-up.
This board can support the ability to program the FPGA for specific requirements. A standard JTAG connector is provided for downloading FPGA object code from the Xilinx development environment. Please note that Texas Instruments does not provide support for any user-designed FPGA functionality beyond the standard functionality that is shipped with the board. Hardware Trigger: The external trigger feature of the Reference Board is designed to enable applications which trigger a data capture.
J155 Override power good C2M (FPGA will output data on FMC) FMC_PG_C2M Mezzanine (ADC0xD1520RB) (ADC12D1X00RFRB) Carrier J156 Override power good M2C (indicates power good from Mez.
Figure 19: Bottom of ADC0XD1520RB showing FMC port 2.8.4 LM95233 Temperature Sensor Using the TI LM95233 temp sensor chip; the ambient, ADC0XD1520 and Xilinx FPGA temperatures can be monitored. The temperature readings are available through the WV-5 software.
3.0 Electrical Specification Power Supply: Nominal = 12V Minimum = 11.0V, Maximum = 12.5V (Voltages outside these levels can cause damage!!) Power Consumption: Nominal = 10 Watts Maximum = 20 Watts ADC Input Signals: Maximum Operating Voltage = see datasheet Recommended/initial (full scale) generator setting = 0 dBm (The maximum level at the signal generator is dependent upon the insertion loss from other hardware before the ADC inputs.
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