Datasheet

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74ACT11074

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH CLEAR AND PRESET

SCAS498A – DECEMBER 1986 – REVISED APRIL 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Inputs Are TTL-Voltage Compatible

Center-Pin V

and GND Configurations to

Minimize High-Speed Switching Noise

EPIC

(Enhanced-Performance Implanted

CMOS) 1- m Process

500-mA Typical Latch-Up Immunity

at 125°C

Package Options Include Plastic

Small-Outline (D) and Shrink Small-Outline

(DB) Packages, and Standard Plastic

300-mil DIPs (N)

description

This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE)

or clear (CLR

) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR

are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs

on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly

related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed

without affecting the levels at the outputs.

The 74ACT11074 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

OUTPUTS

PRE

CLR

CLK D Q Q

L H X X H L

H LXXLH

L LXXHH

H H ↑ HHL

H H ↑ LLH

H H L X Q

†

This configuration is unstable; that is, it does not

persist when either PRE

or CLR returns to its

inactive (high) level.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

1PRE

GND

2PRE

1CLK

1CLR

2CLR

2CLK

D, DB, OR N PACKAGE

(TOP VIEW)

Summary of content (14 pages)

PAGE 1
74ACT11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCAS498A – DECEMBER 1986 – REVISED APRIL 1996 D D D D D D, DB, OR N PACKAGE (TOP VIEW) Inputs Are TTL-Voltage Compatible Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (N) 1PRE
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74ACT11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCAS498A – DECEMBER 1986 – REVISED APRIL 1996 logic symbol† 1PRE 1CLK 1D 1CLR 2PRE 2CLK 2D 2CLR 1 S 14 13 12 2 1Q 3 1Q 6 2Q 5 2Q C1 1D R 7 8 9 10 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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74ACT11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCAS498A – DECEMBER 1986 – REVISED APRIL 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 4.5 V IOH = –50 50 mA VOH 24 mA IOH = –24 IOH = –75 mA† II ICC DICC‡ TA = 25°C TYP MAX 4.4 5.5 V 5.4 5.4 4.5 V 3.94 3.8 5.5 V 4.94 IOL = 75 mA† VI = VCC or GND MAX UNIT V 4.8 3.85 4.5 V IOL = 24 mA MIN 4.4 5.
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74ACT11074 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCAS498A – DECEMBER 1986 – REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION From Output Under Test tw CL = 50 pF (see Note A) 3V 500 Ω Input 1.5 V 1.5 V 0V LOAD CIRCUIT VOLTAGE WAVEFORMS 3V Input (see Note B) 1.5 V 1.5 V 0V tPHL tPLH 3V Timing Input (see Note B) 1.5 V In-Phase Output 50% VCC 0V th tsu Data Input tPLH tPHL 3V 1.5 V 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.
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PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 74ACT11074DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 74ACT11074NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74ACT11074DBR SSOP DB 14 2000 367.0 367.0 38.0 74ACT11074NSR SO NS 14 2000 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.