Datasheet

TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1
PROCESSOR SUPERVISORY CIRCUITS


SGLS143B − DECEMBER 2002 − REVISED JUNE 2008
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
IH(AV)
Average high-level input current
WDI
WDI = V
DD
,
time average (dc = 88%)
120
I
IL(AV)
Average low-level input current
WDI
WDI = 0.3 V, V
DD
= 5.5 V
time average (dc = 12%)
−15
WDI WDI = V
DD
140 190
μ
A
I
IH
High-level input current
MR
MR = V
DD
× 0.7,
V
DD
= 5.5 V
−40 −60
μA
I
Low level input current
WDI WDI = 0.3 V, V
DD
= 5.5 V 140 190
I
IL
Low-level input current
MR
MR = 0.3 V, V
DD
= 5.5 V −110 −160
TPS382x-25
I
Output short-circuit current
RESET
TPS382x-30
V
DD
= V
IT
,
m
a
x
+ 0.2 V,
−400
A
I
OS
Output
short circuit
current
(see Note 4)
RESET
TPS382x-33
V
DD
=
V
IT
,
max
+
0
.
2
V
,
V
O
= 0 V
400
μA
TPS382x-50
O
−800
I
DD
Supply current
WDI and MR unconnected,
Outputs unconnected
15 25 μA
Internal pullup resistor at MR 52 kΩ
C
i
Input capacitance at MR, WDI V
I
= 0 V to 5.5 V 5 pF
NOTE 4: The RESET short-circuit current is the maximum pullup current when RESET is driven low by a μP bidirectional reset pin.
timing requirements at R
L
= 1 MΩ, C
L
= 50 pF, T
A
= 25°C
PARAMETER TEST CONDITIONS MIN MAX UNIT
at V
DD
V
DD
= V
IT−
+ 0.2 V, V
DD
= V
IT-
- 0.2 V 6 μs
t
w
Pulse width
at MR
V
DD
≥ V
IT−
+ 0.2 V, V
IL
= 0.3 x V
DD
, V
IH
= 0.7 x V
DD
1 μs
w
at WDI V
DD
≥ V
IT−
+ 0.2 V, V
IL
= 0.3 x V
DD
, V
IH
= 0.7 x V
DD
100 ns
switching characteristics at R
L
= 1 MΩ, C
L
= 50 pF, T
A
= 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
Watchdog time out
TPS3820
V
DD
≥ V
IT−
+ 0.2 V,
112 200 310 ms
t
tout
Watchdog time out
TPS3823/4/8
V
DD
≥
V
IT
−
+
0
.
2
V
,
See Timing Diagram
0.9 1.6 2.5 s
t
Delay time
TPS3820
V
DD
≥ V
IT−
+ 0.2 V,
15 25 37
ms
t
d
Delay time
TPS3823/4/5/8
V
DD
≥ V
IT
−
+
0
.
2
V
,
See timing diagram
120 200 300
ms
t
PHL
Propagation (delay) time,
high-to-low-level output
MR to RESET delay
(TPS3820/3/5/8)
V
DD
≥ V
IT−
+ 0.2 V,
V
IL
= 0.3 x V
DD
,
V
IH
= 0.7 x V
DD
0.1
μ
s
t
PHL
high-to-low-level output
V
DD
to RESET delay
V
IL
= V
IT-
- 0.2 V,
V
IH
= V
IT-
+ 0.2 V
25
μs
t
PLH
Propagation (delay) time,
low to high level output
MR to RESET delay (TPS3824/5)
V
DD
≥ V
IT−
+ 0.2 V,
V
IL
= 0.3 x V
DD
,
V
IH
= 0.7 x V
DD
0.1
μ
s
t
PLH
low-to-high-level output
V
DD
to RESET delay (TPS3824/5)
V
IL
= V
IT-
- 0.2 V,
V
IH
= V
IT-
+ 0.2 V
25
μs