User's Manual
Table Of Contents
- 1 Device Overview
- Table of Contents
- 2 Revision History
- 3 Device Comparison
- 4 Terminal Configuration and Functions
- 5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Power Consumption Summary
- 5.5 General Characteristics
- 5.6 Antenna
- 5.7 1-Mbps GFSK (Bluetooth low energy) – RX
- 5.8 1-Mbps GFSK (Bluetooth low energy) – TX
- 5.9 2-Mbps GFSK (Bluetooth low energy) – RX
- 5.10 2-Mbps GFSK (Bluetooth low energy) – TX
- 5.11 IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) – RX
- 5.12 IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) – TX
- 5.13 24-MHz Crystal Oscillator (XOSC_HF)
- 5.14 32.768-kHz Crystal Oscillator (XOSC_LF)
- 5.15 48-MHz RC Oscillator (RCOSC_HF)
- 5.16 32-kHz RC Oscillator (RCOSC_LF)
- 5.17 ADC Characteristics
- 5.18 Temperature Sensor
- 5.19 Battery Monitor
- 5.20 Continuous Time Comparator
- 5.21 Low-Power Clocked Comparator
- 5.22 Programmable Current Source
- 5.23 DC Characteristics
- 5.24 Thermal Resistance Characteristics for MOH Package
- 5.25 Timing Requirements
- 5.26 Switching Characteristics
- 5.27 Typical Characteristics
- 6 Detailed Description
- 7 Application, Implementation, and Layout
- 8 Device and Documentation Support
- 9 Mechanical Packaging and Orderable Information
- Important Notice
PRODUCTPREVIEW
26
CC2650MOD
SWRS187 –AUGUST 2016
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Detailed Description Copyright © 2016, Texas Instruments Incorporated
6.3 Main CPU
The SimpleLink CC2650MOD Wireless MCU contains an ARM Cortex-M3 (CM3) 32-bit CPU, which runs
the application and the higher layers of the protocol stack.
The CM3 processor provides a high-performance, low-cost platform that meets the system requirements
of minimal memory implementation, and low-power consumption, while delivering outstanding
computational performance and exceptional system response to interrupts.
CM3 features include:
• 32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications
• Outstanding processing performance combined with fast interrupt handling
• ARM Thumb
®
-2 mixed 16- and 32 bit instruction set delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the
range of a few kilobytes of memory for microcontroller-class applications:
– Single-cycle multiply instruction and hardware divide
– Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral
control
– Unaligned data access, enabling data to be efficiently packed into memory
• Fast code execution permits slower processor clock or increases sleep mode time
• Harvard architecture characterized by separate buses for instruction and data
• Efficient processor core, system, and memories
• Hardware division and fast digital-signal-processing oriented multiply accumulate
• Saturating arithmetic for signal processing
• Deterministic, high-performance interrupt handling for time-critical applications
• Enhanced system debug with extensive breakpoint and trace capabilities
• Serial wire trace reduces the number of pins required for debugging and tracing
• Migration from the ARM7™ processor family for better performance and power efficiency
• Optimized for single-cycle flash memory use
• Ultra-low power consumption with integrated sleep modes
• 1.25 DMIPS per MHz
6.4 RF Core
The RF Core contains an ARM
®
Cortex
®
-M0 processor that interfaces the analog RF and base-band
circuitries, handles data to and from the system side, and assembles the information bits in a given packet
structure. The RF core offers a high level, command-based API to the main CPU.
The RF core is capable of autonomously handling the time-critical aspects of the radio protocols (802.15.4
RF4CE and ZigBee, Bluetooth low energy) thus offloading the main CPU and leaving more resources for
the user application.
The RF core has a dedicated 4KB SRAM block and runs initially from separate ROM memory. The ARM
Cortex-M0 processor is not programmable by customers.