User's Manual

PRODUCTPREVIEW
17
CC2650MOD
www.ti.com SWRS187 –AUGUST 2016
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SpecificationsCopyright © 2016, Texas Instruments Incorporated
(1) °C/W = degrees Celsius per watt.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘ
JC
] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.
(3) m/s = meters per second.
5.24 Thermal Resistance Characteristics for MOH Package
NAME DESCRIPTION °C/W
(1) (2)
AIR FLOW (m/s)
(3)
RΘ
JC
Junction-to-case 20.0
RΘ
JB
Junction-to-board 15.3
RΘ
JA
Junction-to-free air 29.6 0
RΘ
JMA
Junction-to-moving air 25.0 1
Psi
JT
Junction-to-package top 8.8 0
Psi
JB
Junction-to-board 14.8 0
(1) For smaller coin cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor (see
Section 7.1.1) must be used to ensure compliance with this slew rate.
(2) Applications using RCOSC_LF as sleep timer must also consider the drift in frequency caused by a change in temperature (see
Section 5.16).
(3) T
A
= –40°C to +85°C, V
DDS
= 1.7 V to 3.8 V, unless otherwise noted.
(4) T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted. Device operating as SLAVE. For SSI MASTER operation, see Section 5.26.
(5) Refer to SSI timing diagrams Figure 5-1, Figure 5-2, and Figure 5-3.
5.25 Timing Requirements
MIN NOM MAX UNIT
Rising supply-voltage slew rate 0 100 mV/µs
Falling supply-voltage slew rate 0 20 mV/µs
Falling supply-voltage slew rate, with low-power flash settings
(1)
3 mV/µs
Positive temperature gradient in standby
(2)
No limitation for negative
temperature gradient, or
outside standby mode
5 °C/s
CONTROL INPUT AC CHARACTERISTICS
(3)
RESET_N low duration 1 µs
SYNCHRONOUS SERIAL INTERFACE (SSI)
(4)
S1 (SLAVE)
(5)
t
clk_per
SSIClk period 12 65024
system
clocks
S2
(5)
t
clk_high
SSIClk high time 0.5 t
clk_per
S3
(5)
t
clk_low
SSIClk low time 0.5 t
clk_per
(1) Device operating as MASTER. For SSI SLAVE operation, see Section 5.25.
(2) Refer to SSI timing diagrams Figure 5-1, Figure 5-2, and Figure 5-3.
5.26 Switching Characteristics
Measured on the TI CC2650EM-5XD reference design with T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
WAKEUP AND TIMING
Idle → Active 14 µs
Standby → Active 151 µs
Shutdown → Active 1015 µs
SYNCHRONOUS SERIAL INTERFACE (SSI)
(1)
S1 (TX only)
(2)
t
clk_per
(SSIClk period) One-way communication to SLAVE 4 65024
system
clocks
S1 (TX and RX)
(2)
t
clk_per
(SSIClk period) Normal duplex operation 8 65024
system
clocks