User Guide

WE866C6 Hardware Design Guide
1VV0301658 Rev. 1 Page 14 of 58 2020-06-16
3. PINS ALLOCATION
Pin Type Definition
Type
Description
DI
Digital Input
DO
Digital Output
PD
Pull-Down
PU
Pull-Up
OD
Open-Drain Output
B
Bi-Directional
AI
Analog/RF Input
AO
Analog/RF Output
P
Power Input
Note: Pins directions are with respect to the WE866C6 module.
Pin-out
Pin
Pin Name
Pin Reference
Voltage
Pin
Type
Pin Description
BT UART interface
B3
BT_CTS
VIO
DI
Bluetooth HCI-UART CTS signal
B4
BT_RTS
VIO
DO
Bluetooth HCI-UART RTS signal
A5
BT_RXD
VIO
DI
Bluetooth HCI-UART RXD signal
A4
BT_TXD
VIO
DO
Bluetooth HCI-UART TXD signal
BT PCM interface
C6
BT_I2S_SDI
VIO
DI, PU
Bluetooth PCM/I2S Input signal, Internal Pull-Up
C5
BT_I2S_WS
VIO
B
Bluetooth PCM/I2S Frame Sync signal
D5
BT_I2S_SCK
VIO
B, PD
Bluetooth PCM/I2S Bit CLK signal
D6
BT_I2S_SDO
VIO
DO
Bluetooth PCM/I2S output signal
Low power Clock signal
B5
LF_CLK_IN
VIO
DI, PD
External low–power 32.768 kHz clock input
Host wake pins
D4
WOW
VIO
OD,
PU
Wake on Wireless. WIFI/BT Wakeup host.
Active Low, Internal Pull-Up
SDIO 3.0 interface
D7
SDIO_CLK
VIO
DI, PU
SDIO clock signal Input, Internal Pull-Up
E7
SDIO_CMD
VIO
B
SDIO CMD line signal
C7
SDIO_D0
VIO
B
SDIO data bus D0
B6
SDIO_D1
VIO
B
SDIO data bus D1
A6
SDIO_D2
VIO
B, PU
SDIO data bus D2, Internal Pull-Up
B7
SDIO_D3
VIO
B
SDIO data bus D3
Coexistence and control
signals
C3
LTE_UART_RX
VIO
DI, PU
Secondary UART - LTE coexistence UART RXD
/ AUX UART RXD
C4
LTE_UART_TX
VIO
DO
Secondary UART - LTE coexistence UART_TXD
/ AUX_UART_TXD