PSM Application Note r2
Table Of Contents
- Notice
- Copyrights
- Computer Software Copyrights
- Usage and Disclosure Restrictions
- APPLICABILITY TABLE
- CONTENTS
- 1. Introduction
- 2. OVERVIEW
- 3. PSM DESCRIPTION
- 4. PINS ALLOCATION
- 5. Glossary and Acronyms
- 6. Document History
80471NT11483A Rev. 2 Page 17 of 24 2017-06-06
4.5.2. Digital IOs Supply Guidelines
The Digital IO section requires to be supplied applying a 1.8V power supply to the
VDDIO_IN input.
In a normal Application design, this is done connecting the VDDIO_IN to the
VAUX/PWRMON line.
Using this supply line we have two effects:
• When in PSM=2 the VAUX is switched off so the Host has to ensure to avoid
applying any high logic level to the IOs that could damage the module.
• VAUX has a quiescent current of ~40uA and if it is kept alive also VSIM is kept alive
(total of ~80uA)
During the PSM modes the host should ignore the value of the signals coming from the
LE866 (as all pins are turned to High Z if VDD_IO_IN is available or to non defined state if
VDDIO_IN is shut off)