PSM Application Note r2
Table Of Contents
- Notice
- Copyrights
- Computer Software Copyrights
- Usage and Disclosure Restrictions
- APPLICABILITY TABLE
- CONTENTS
- 1. Introduction
- 2. OVERVIEW
- 3. PSM DESCRIPTION
- 4. PINS ALLOCATION
- 5. Glossary and Acronyms
- 6. Document History
80471NT11483A Rev. 2 Page 15 of 24 2017-06-06
Logic Levels Specification
ABSOLUTE MAXIMUM RATINGS:
Parameter Min Max
Input level on any digital pin (CMOS 1.8) with respect
to ground
-0.3V
VDDIO_IN
+0.3V
Input level on any digital pin (CMOS 1.8) with respect
to ground when VDDIO is not supplied
-0.3V 0.3V
OPERATING RANGE - INTERFACE LEVELS (1.8V CMOS):
Parameter Min Max
Input high level 1.55V 1.9V
Input low level 0V 0.35V
Output high level 1.35V 1.8V
Output low level 0V 0.8V
WARNING:
If VDDIO_IN line is not powered (i.e. during the sleep states in PSM=2 when
supplied by VAUX, during transition phases BOOT, RESET etc. and when the
module is unsupplied) it is important to avoid back powering the digital pins.
Exceeding the absolute maximum ratings could damage permanently the
module.