PSM Application Note r2
Table Of Contents
- Notice
- Copyrights
- Computer Software Copyrights
- Usage and Disclosure Restrictions
- APPLICABILITY TABLE
- CONTENTS
- 1. Introduction
- 2. OVERVIEW
- 3. PSM DESCRIPTION
- 4. PINS ALLOCATION
- 5. Glossary and Acronyms
- 6. Document History
80471NT11483A Rev. 2 Page 14 of 24 2017-06-06
PSM SIGNALS DETAIL
4.3.1. PSM_WAKE
PSM_WAKE is the only pin that can wake the system from the PSM Mode.
It is normally Low and should be set to High to wake up the module.
NOTE:
The pin requires to add a pull down resistor on the application.
4.3.2. PSM_STATUS
PSM_STATUS is a GPIO controlled by SW that is low during the PSM mode and high during
regular operation. This pin is used for the LE866/Host Controller protocol when
entering/exiting PSM state.
4.3.3. PSM_ENA_OUT
PSM_ENA_OUT is low during normal operation and open drain during the PSM state. It
may be used to enable/disable the unnecessary supplies to the different system
components when entering exiting the PSM state.
4.3.4. RESET*
RESET* disables the entire integrated power management and is used as a power reset.
4.3.5. VDDIO_IN
VDDIO_IN is the Digital IO supply Input pin.