xE922-3GR Hardware User Guide 1VV0301272 Rev.0.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 APPLICABILITY TABLE PRODUCT HE922-3GR WE922-3GR APPLICABILITY TABLE 1 Reproduction forbidden without written authorization from Telit Communications S.p.A. - All Rights Reserved.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE Notice While reasonable efforts have been made to assure the accuracy of this document, Telit assumes no liability resulting from any inaccuracies or omissions in this document, or from use of the information obtained herein. The information in this document has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies or omissions.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Usage and Disclosure Restrictions License Agreements The software described in this document is the property of Telit and its licensors. It is furnished by express license agreement only and may be used only in accordance with the terms of such an agreement. Copyrighted Materials Software and documentation are copyrighted materials. Making unauthorized copies is prohibited by law.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Contents 1. 2. Introduction ..................................................... 9 1.1. Scope ....................................................... 9 1.2. Audience ..................................................... 9 1.3. Contact Information, Support ....................................... 10 1.4. Text Conventions............................................... 10 1.5. Supporting documents ..........................................
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 4.2. Recommended operating conditions .................................. 39 4.3. Logic Level Specifications ........................................ 39 Power supply .................................................... 41 5. 5.1. Input supply .................................................. 41 5.2. Output supply ................................................. 42 5.2.1. Linear voltage regulators .................................. 5.2.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 10.2. LVDS..................................................... 62 10.3. Backlight control ............................................. 64 10.4. LED_CURSINK ............................................. 65 10.5. Touch panel ................................................. 66 11. Camera interface ............................................... 67 12. Peripheral interfaces ............................................. 71 12.1. I2C ...
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 16.2. WiFi/BT Antenna Requirements ................................... 93 16.3. GNSS Antenna Requirements .................................... 93 17. 16.3.1. 16.3.2. 16.3.3. Combined GNSS Antenna .......................................... 94 Linear and Patch GNSS Antenna ..................................... 94 Front End Design Considerations ..................................... 94 16.3.4. 16.3.5. GNSS Antenna - PCB Line Guidelines ......
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 1. Introduction 1.1. Scope The aim of this document is to introduce Telit xE922-3GR modules as well as present possible and recommended hardware solutions useful for developing a product based on the xE922-3GR modules. All the features and solutions detailed are applicable to all xE922-3GR, where “xE922-3GR” refers to the modules listed in the applicability table.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 1.3. Contact Information, Support For general contact, technical support, to report documentation errors and to order manuals, contact Telit’s Technical Support Center (TTSC) at: TS-NORTHAMERICA@telit.com if located in North America For other regions, Collabnet Telit web portal can be used at https://teamforge.telit.com (account can be asked at support.collabnet@telit.com Alternatively, use: http://www.telit.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 1.5. Supporting documents · 1VV0301249_EVB USER GUIDE.pdf · 1VV0301285_IFBD HW User Guide xE922-3GR.pdf · 1VV0301324_MMI_EXT_CARD_xE922_3GR_HW USER GUIDE · 80504NT11473A Thermal Guidelines.pdf For further detailed information, HW/SW user manuals and application notes related to the INTEL chipset applied for this RF module, please consult Intel Business Link Support (IBL): https://businessportal.intel.com 1.6.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 2. General Product Description 2.1. Overview Telit’s module family xE922-3GR is based on Intel’s IoTG Atom x3 Quad Core processor dual chip platform. DBB : SoC Atom x3 · CPU: Quad Core (Silvermont) 1.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 · GNSS · Audio · Analog measurement · Power management The module incorporates the following key technologies: · 2G/3G cellular subsystem · GNSS subsystem · WiFi and Bluetooth subsystems · Display subsystem · Camera subsystem · Audio subsystem · Power management xE922-3GR is designed for commercial (0C to70C) & industrial (extended temperature -40C to +85C) markets quality needs.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 2.2. General Functionality and Main Features The xE922-3GR family of IoT modules features 2G/3G modem, GNSS and WiFi/BT connectivity together with an on-chip powerful application processor and a rich set of interfaces. This overview sums all key interfaces offered by the module , consult the documentation on INTEL’s IBL supporting website for actual implementation state.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 o 1x mono earpiece output o 1x mono speaker (classD 700mW/3.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 · o Reduction of switching power consumption by clock gating. o Reduction of leakage power by switching off non active logic.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 o Exponentiation accelerator – supports RSA(1024.2048) o Hashing engines : MD5, HMAC, SHA1/256 o True-RNG · Secure memory : isolated memory region IMR for secure VM · Secure boot : root of trust is SEC ROM · Content protection : Widevine Level 1 DRM ( HW protected Video Path) J) Rich set of module I/O interfaces, including: · SDIO: SD 3.0, 1x 4bit, speed up to DDR50 only 1.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Mode Freq. TX (MHz) Freq. RX (MHz) Channels TX - RX offset GSM 850 824.2 ~ 848.8 869.2 ~ 893.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 - Data retrieval to prevent terror attacks - 2.5. Sensitivity · 3G =< -110 dBm · 2G CS1 =< -111 dBm · 2G CS4 =< -103 dBm Reproduction forbidden without written authorization from Telit Communications S.p.A. - All Rights Reserved.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 2.6.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 2.7. Environmental requirements 2.7.1. Temperature range Operating Temperature Range -20 ~ +55°C : This range is defined by 3GPP (the global standard for wireless mobile communication). Telit guarantees its modules to comply with all the 3GPP requirements and to have full functionality of the module with in this range.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 2.8. 2.8.1. xE922-3GR Mechanical Specifications Dimensions The Telit xE922-3GR module overall dimensions are: 2.8.2. • Length: 34 mm, +/- 0.15 mm Tolerance • Width: 40 mm, +/- 0.15 mm Tolerance • Thickness: 3.0 mm, +/- 0.15 mm Tolerance Weight The nominal weight of the xE922-3GR module is 9.7 gram. 2.8.3.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 3. xE922-3GR Module pin out 3.1. PAD PIN table Signal I/O descriptions Type USB 2.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 E2 SD_CLK O G2 SD_CMD I/O MMC card clock CMOS_1.8/3V MMC card command CMOS_1.8/3V SDIO Interface L4 SDIO_CLK I/O CLK CMOS 1.8V P3 SDIO_CMD I/O CMD CMOS 1.8V P1 SDIO_DAT0 I/O SD0 CMOS 1.8V N2 SDIO_DAT1 I/O SD1 CMOS 1.8V M3 SDIO_DAT2 I/O SD2 CMOS 1.8V N4 SDIO_DAT3 I/O SD3 CMOS 1.8V USIF 1 (UART/SPI) W5 USIF1_RXD I UART1 / SPI1 Serial data input CMOS 1.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 B5 GPIO67_EINT0 I/O GPIO / External IRQ CMOS 1.8V F3 GPIO72_EINT9 I/O GPIO / External IRQ CMOS 1.8V B3 GPIO73_EINT10 I/O GPIO / External IRQ CMOS 1.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 AA4 VAUX_3P0V - AA20 V_RTC - Auxiliary 3.
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xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 LGA Pads Layout 3.2.
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xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 4. Electrical specifications 4.1. Absolute maximum ratings – not operational A deviation from listed below values range may harm the xE922-3GR module. Symbol 4.2. Parameter Min Max Unit VBATT battery supply voltage on pin VBATT -0.3 +5.5 [V] VBATT_PA battery supply voltage on pin VBATT_PA -0.3 +6.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 For 1.8V CMOS signals: Absolute Maximum Ratings - Not Functional xE922-3GR Parameter Min Max Input level on any -0.3V +2.16V digital pin when on Input voltage on -0.3V +2.16 V analog pins when on VIH Operating Range - Interface levels (1.8V CMOS) Unit xE922-3GR Parameter Min Max [V] Input high level 1.3V 2.1V VIL VOH VOL Input low level Output high level Output low level IIL -0.3V 1.6V 0.5V condition [V] [V] Ioh= 0.1 mA 0.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 5. Power supply 5.1. Input supply There are 2 input power supplies defined on the xE922-3GR module, V_BAT, V_BAT_PA. V_BAT_PA pin supplies transmit RF front end (RFFE) power amplifiers (PA) of the cellular network (2G/3G) connection feature of the module. V_BAT pin supplies the remaining module circuitry, distributed via an internal power management unit (PMU). Although defined separately, V_BAT and V_BAT_PA can be connected together.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Both V_BAT_PA and V_BAT are protected by Zener transient voltage suppressor diodes internal the module. Although the internal transient suppressor also protects for reverse polarized input supply application, its max power dissipation is limited as well. For performance specification of this protection please consult the datasheet. (DF3A6.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 5.2.1.2. parameter VAUX_2P85V symbol value Min External cappacitor Cext Cappacitor ESR R_esr Output voltage Vreg Output Ireg Current max Current Imax unit condition Typ max 1000 1400 nF 100 ohm 100 Hz 0.05 ohm 1 MHz…30MHz 2.85 V Configurable 1.8/2.5/2.8/2.85V 225 mA 1.8 400 mA Limitation Default value Default state 2.85V OFF Default value Default state 50% nominal LDO voltage 5.2.1.3.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 The datasheet of the eMCP specifies a maximum current consumption on this powersupply line of about 150mA (read operation). Care should be exercised to limit the total power consumption, to keep heat dissipation limited: Power_dissipation = (V_BAT-3.0V) x (150mA_max+I_external) 5.2.1.4. VSIM1/2 parameter symbol value Min External cappacitor Cext Cappacitor ESR R_esr Output voltage Vreg 1.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Current max Pull-downr resistor Rpd Switching F_dcdc -3% 3.2 200 ohm +3% MHz DC/DC is OFF frequency Note: 1V8_OUT is also applied internally the module feeding several I/O peripherals, memory interface and analog RF parts (depending on use case). Care should be exercised to keep external current dissipation limited in order not to exceed the maximum output current of the DC/DC regulator.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 standby Flight Mode 2.6 WLAN Idle associated (3G cell registered) 8.6 2G Standby, DRX5 GSM850 4.8 GSM900 4.8 DCS1800 4.8 PCS1900 6.3 3G Standby, DRX7 Data traffic B1 4 B2 4.7 B5 4.1 B8 4.1 GPRS 4TX(gamma10)/1RX PS GSM850 212 GSM900 220 DCS1800 173 PCS1900 185 3G 24dBm RMC 12.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Browsing Imaging GNSS BT Video Streaming HTML5 WLAN -H.264 -720p 776 Video Streaming HTML5 3G -H.264 -720p chrome52 959 Browsing Chrome HTML5 -WLAN 448 Browsing Chrome HTML5 -3G 560 User mode image capture, 3G idle TBD Video Recording, HD 720p 30fps AVC baseline 3.1, 1.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 The following table gives an overview of V_RTC minimum voltage level requirements in order to keep RTC running: condition minimum V_RTC [V] min Typ max room temperature 0.8 1.1 -40 to +125deg 0.9 1.2 So typically at room temperature a voltage difference of 2.3V – 0.8V = 1.5V is available for buffering the RTC supply in case V_BAT is removed.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 6. Power ON/OFF and reset control 6.1. Power On Once power applied to the V_BAT, the power on can be triggered by four possible events: · · · 6.1.1. ON_OFF key event (+ application of power to system with ‘first connect’ enabled) External charger detection (CHG_POK) RTC alarm ON_OFF key action If the ON_OFF key is forced by external circuitry to V_RTC, the sytem startup procedure begins.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 6.1.2. Switching ON due to charging If an external charger is detected the system startup procedure begins. An external charger can be detected by LOW level detection on CHG_POK and / or CHG_INT input pins. Both pins have an internal pullup applied to V_RTC. (See chapter 7.2 for charger IC connections) 6.1.3. Switching on due to RTC alarm The real time clock can generate a wake-up signal called RTC alarm.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 7. Battery management The xE922-3GR chipset supports an (optional) complete battery management solution based on external charger IC interfacing by the following dedicated charging control lines.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Minimize parasitic resistance in the current path by using thick copper traces between sense resistor and PCB ground and negative battery terminal respectively. The fuel gauge FG_IBATP/N signal pair should be routed as differential and isolated from aggressors (like clocks, DC/DC switching nodes) to minimize noise interference. A low pass filter 4.7k/1uF is present inside the xE922-3GR module.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 The CHG_POK line (active LOW, internal pullup to always_on domain V_RTC) wakes the system once a valid input supply source is present. It has the same effect as the ON_OFF key event to initiate a power-up sequence. The CHG_INT line (active LOW, internal pullup to always_on domain V_RTC) signals charger state change or failure, and replaces, in case not used, the CHG_POK function.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 7.2.2. Battery/charger-less operation In case the xE922-3GR module is applied directly from a DC source supply, without battery and/or external charger IC, the charger specific interface signals should be connected as indicated in the next picture. Since VBATMEAS and POK signals are still used in the power on sequencing / boot process, it is important to have the following minimum connections implemented.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 8. USIM interface xE922-3GR supports two external USIM interfaces (dual volt 1.8/3V) compatible with ISO 7816-3 IC Card standard. PAD Signal I/O descriptions Type SIM card interface 1 AM5 VSIM1 - External SIM signal 1 – Power supply for the SIM 1.8 / 2.85V AR6 SIMCLK1 O External SIM signal 1 – Clock 1.8 / 2.85V AN10 USIM1_DETECT I External SIM signal 1 – Card detect (Active low) CMOS 1.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 NOTE FOR R1: The resistor value on SIMIO pulled up to SIMVCC should be defined accordingly in order to be compliant with 3GPP specification for USIM electrical testing. Rise/fall time of SIMIO line should not exceed 1 µs. The xE922-3GR module contains an internal 4.7 kOhm pull-up resistor on SIMIO which should be sufficient in most applications. For C1 a value of 1uF is recommended with the XE922-3GR product.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 9. USB port The xE922-3GR module includes a Universal Serial Bus (USB) transceiver, which operates at USB high-speed (480Mbits/sec). It can also operate with USB full-speed (12Mbits/sec) hosts. It is compliant with the USB 2.0 ‘DRD’ dual role specification, 15 endpoints, and can be used control and data transfers as well as for diagnostic monitoring and firmware update. The interface does not support ‘OTG’ (HNP) to switch roles on the fly.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 At least Test point of the USB signals are required since the USB physical communication is needed in the case of SW update. Routing guide lines for the display USB2.0 interface: The next figure shows a typical signal traject with different sub trajects.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Guidelines for sub trajects: parameter module main Bi1 Bi2 AOB stub Transmission line segment L1 (MS/SL) L2 (SL) L3 (MS) L4 (MS) L5(SL) Lstub Max. length [mm] 25.4 101.6 12.7 25.4 101.6 5.1 Actual xE922-3GR module signal trace (L1) implementation: signal name module trace length [mm] Number of microvias on the module USB_DP 5.06 3 USB_DN 5.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 10. Display interface The xE922-3GR supports a display according following 3 interface types: · MIPI-DSI (4-lane, GPIO’s including tearing effect timing control) · LVDS (4-lane) On top of this display interface the module also features backlight control (CABC input, BL feedback input, BL drive output) and I2C port to control a touch panel IC.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Recommended routing guidelines for the whole MIPI-DSI signal traject: parameter guideline Characteristic impedance (stripline / microstrip) 100 ohm differential 10%(SL) 15%(MS) Trace spacing : between differential pairs or between 5xh (SL) 7xh (MS) differential pair and other signals (h = dielectric height) Total length Min. 50.8 mm / Max. 152.4 mm (MS/SL) (module (L1+L2) + carrier(L3)+add-on pcb(L4) + FPC cable(L5)) Max.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Actual xE922-3GR module signal trace (L1+L2) implementation: signal name module trace length [mm] Number of microvias on the module DSI_CLKN 9.88 2 DSI_CLKP 9.65 2 DSI_DN0 7.39 2 DSI_DP0 7.15 2 DSI_DN1 9.09 2 DSI_DP1 9.28 2 DSI_DN2 8.60 2 DSI_DP2 8.43 2 DSI_DN3 12.16 2 DSI_DP3 12.01 2 10.2.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 S21 LVDS_TCLK1N AO LVDS Clock Negative Analog Routing guide lines for the display LVDS interface: The next figure shows a typical signal traject with different sub trajects.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Guidelines for off-module sub trajects: parameter Carrier board Addon board Transmission line segment L3 L4 Length [mm] 82.5 (MS/SL) Max. 203.2 – (L1+L2+L3) Actual xE922-3GR module signal trace (L1+L2) implementation: signal name module trace length [mm] Number of microvias on the module LVDS_TCLK1N 10.47 2 LVDS_TCLK1P 10.46 2 LVDS_TA1N 9.12 2 LVDS_TA1P 9.31 2 LVDS_TB1N 8.25 2 LVDS_TB1P 8.51 2 LVDS_TC1N 8.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 A typical application of the backlight control is drawn in below figure . LEDDRV controls the gate of an external NFET with PWM signal. During first time period t1 the inductor L is charged via the n-channel FET closed , while during second period t2 the inductor L is discharged via the parallel LED’s. CABC = Content Adaptive Backlight Control input from external backlighting control IC.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 10.5. PAD Touch panel Signal I/O descriptions Type Touch Screen interface AD17 TP_SDA I/O Touch panel I2C Data CMOS 1.8V AB17 TP_SCL I/O Touch panel I2C Clock CMOS 1.8V F7 TP_RESET I/O Touch panel Reset CMOS 1.8V F11 TP_IRQ I/O Touch panel Interrupt CMOS 1.8V A dedicated I2C bus and control lines are foreseen to interface with an external touch panel control IC.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 11. Camera interface The xE922-3GR module offers two CIF camera interfaces. MIPI CSI-2 compliant, utilizing MIPI DPHY as physical layer. Max rate of bit clock of a DPHY lane is defined as 500MHz, or equivalent datarate 1Gbps.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Main camera: · · · High resolution up to 13Mpixel /15 fps 4-lane MIPI CSI-2 up to 550Mbps/lane data rate ( limited by ISP throughput) Secondary camera: · Low resolution up to 5Mpixel · 1-lane MIPI CSI-2 · up to 1Gbps/lane data rate The cameras cannot be used simultaneously, only 1 at the time.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Recommended routing guidelines for the whole MIPI-CSI-2 signal traject : parameter guideline Characteristic impedance (stripline / microstrip) 100 ohm differential 10%(SL) 15%(MS) Trace spacing : between differential pairs or between 5xh (SL) 7xh (MS) differential pair and other signals (h = dielectric height) Total length Min. 45.7 mm / Max. 203.2 mm (MS/SL) (add-on pcb (L1)+ carrier (L2)+ (module (L3+L4)) Max.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 CSI1_DP1 7.48 2 CSI1_DN2 7.77 2 CSI1_DP2 7.52 2 CSI1_DN3 7.31 2 CSI1_DP3 7.26 2 signal name module trace length [mm] Number of microvias on the module CSI2_CLKN 10.04 2 CSI2_CLKP 10.26 2 CSI2_DN 10.46 2 CSI2_DP 10.7 2 Reproduction forbidden without written authorization from Telit Communications S.p.A. - All Rights Reserved.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 12. 12.1. Peripheral interfaces I2C The xE922-3GR offers in total four I2C bus interfaces. 1V8 IO, standard/fast mode SCLK 100 kHz/400 kHz. The below table gives an overview and indicates the assigned functions that are ‘reserved’ for each I2C bus port. PAD Signal I/O descriptions Type AM17 CAM_I2C_SDA I/O Camera I2C Data CMOS 1.8V AP17 CAM_I2C_SCL I/O Camera I2C Clock CMOS 1.8V AD17 TP_SDA I/O Touch panel I2C Data CMOS 1.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 12.2. USIF xE922-3GR offers two ‘Universal Serial Interface’ ports, configurable either as SPI or UART · · PAD USIF1 :SPI (up to 48MHz) / UART USIF2 :SPI (up to 26MHz) / UART Signal I/O descriptions Type USIF 1 (UART/SPI) W5 USIF1_RXD I UART1 / SPI1 Serial data input CMOS 1.8V Y5 USIF1_TXD O UART1 / SPI1 Serial data Output CMOS 1.8V S5 USIF1_SCLK I/O UART1 RTS / SPI1 SCLK CMOS 1.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Actual xE922-3GR module signal trace (L1) implementation USIF1: signal name module trace length [mm] Number of microvias on the module USIF1_SCLK 24.8 3 USIF1_RXD 20.8 3 USIF1_TXD 20.2 3 USIF1_CS 22.2 3 Actual xE922-3GR module signal trace (L1) implementation USIF2: signal name module trace length [mm] Number of microvias on the module USIF2_SCLK 60.8 3 USIF2_RXD 59.2 3 USIF2_TXD 59.4 3 USIF2_CS 58.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 12.3. SDMMC/SDIO SDIO: SD 3.0, 1x 4bit, speed up to DDR50 (clk 48MHz) / SDR50 (clk 96MHz), only 1.8V supported SDMMC: SD 3.0, 1x 4bit, default mode 26MHz, including power supply VDD_SD (fixed to 2.9V) and card detect Note: In case SDMMC 1.8V support is needed, an external 3.0V voltage regulator should be added (ENABLE pin controlled by VDD_SD line), to supply card VDD pin of the card holder.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 A typical diagram for SDMMC card connection is shown in below figure. Series resistor R1 place holder is recommended for tuning high speed CLK signal, typ.27 Ohm. Internal regulator VDD_SD supports dual voltage level 2.9V (default)/1.8V, with current rating max 255 mA. Maximum decoupling capacitance C1 is up to 5 uF (including the internal 1uF decoupling already present). In case ESD protection to be applied, use high speed device < 2pF.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Recommended routing guidelines for the whole SDMMC/SDIO signal traject: parameter Characteristic microstrip) guideline impedance (stripline / 50 ohm single ended 10%(SL) 15%(MS) Trace spacing (h = dielectric height) 2xh (SL) 3xh (MS) Total length Min. 12.7 mm / Max. 88.9 mm (MS/SL) (module (L1) + carrier(L2)) Max.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 signal name module trace length [mm] Number of microvias on the module SD_CLK 37.86 4 SD_CMD 37.26 4 SD_DAT0 37.79 4 SD_DAT1 36.54 4 SD_DAT2 35.72 4 SD_DAT3 36.49 4 12.4.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 13. General purpose I/O The following table gives an overview of the xE922-3GR pins that are ‘suggested’ for general purpose I/O use case: Reset state PAD Signal I/O descriptions Type AV8 GPIO0_EINT5 I/O CMOS 1.8V AT8 GPIO1_EINT2 I/O AS11 GPIO5_EINT7 I/O GPIO / External IRQ GPIO / External IRQ, Used for SoC USB ID WU from Sleep GPIO / USB_FAULT IRQ CMOS 1.8V T/PD G10 GPIO44 I/O GPIO CMOS 1.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Each SoC pad’s characteristics are controlled by a peripheral called PCL (Port Control Logic). In the next page table a ‘complete’ overview of all PCL muxing options for ‘all DBB pins externally available’ on the xE922-3GR module LGA pinout is detailed out.
T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PD T/PU T/PU T T L L L L L L I I I I I I I I I I I I I I I I I O O O O O I I I I I I O I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I G3 G2 G5 G4 E12 E10 A12 A13 U6 V5 Y5 W4 AA4 Y4 T2 T3 U2 T4 T5 T1 E13 M1 N3 N5 K4 K5 N4 M4 K3 M3 M2 N1 F2 M5 K1 G1 J3 K2 J4 J1 J5 J2 H2 R1 R2 L2 N2 R4 R3 R5 P2 B14 I A15 I I I C21 D21 E17 C19 D19 E20
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 14. Debug / flash interfaces For debugging and/or flashing FW to the xE922-3GR module, several interfaces are available. Please refer to EVB documentation for example of debug connector implementations. 14.1. USB2.0 HS This interface can be used as image flash download and debug interface (ADB debug interface) 14.2. USIF2 UART configuration, can be used for SW logging UART.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 15. Audio Note: The audio interface description below explains all possible audio path routing available by the module’s LGA pin map. Currently the FW does not allow changing the preferred audio path on the fly, it is hard coded. The default audio configuration is: · Audio in : analog microphone MICP/N1 · Audio out : analog headphone HP_OUT_R/L Please consult Intel IBL support for other audio path configuration support. 15.1.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 The following figure shows a top level view of the analog Audio frontend (AFE) of xE92-3GR ABB/PMU. The IDI connects the ABB to the Audio DSP/DBB. Note: All measurements done like described in AES-17 standard method for digital audio engineering. The values included in the below tables are extracted from to the chipset datasheet. 15.1.1.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Parameters audio ADC: Parameter Min Typ Max Unit condition Bit width 16 bit BW 20 Hz Lower limit Upper limit sample rate 4 20 kHz 2 4 MHz Parameters decimation filter Sample rate fs mode Passband corner Passband ripple Stopband Stopband attenuation 8 kHz Narrowband speech >3.4 kHz < 1dB 4.0-35 kHz 80 dB 16 kHz Wideband speech >6.8 kHz < 1dB 8.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 The following figure shows typical single ended connection concept for electret microphones (AC coupling value for low cut off frequency @ 300Hz): The MICP/MICN should be routed close together in order to minimize interference noise. Differential mode can be interesting when feeding the MIC input from a differential pre-amplifier.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Parameters VMIC_BIAS supply: Parameter Min VMIC_BIAS Typ Max 1.9..2.2 Unit V I_out 4.0 mA Noise 4 uVrms R_load 1 PSSR 15.1.2. condition 300-3900Hz kOhm 75 dB Analog OUT The analog audio-out consists of two DAC’s followed by post filter, and finally the output stage. The DAC is preceeded by digital interpolation filter of which oversampling ratio depends on respective sampling rate.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Parameters interpolation filter Sample rate fs mode Passband corner Passband ripple Stopband Stopband attenuation 8 kHz Narrowband speech >3.4 kHz < 0.5dB 4.6-50 kHz 96 dB 16 kHz Wideband speech >6.8 kHz < 0.5dB 9.2-50 kHz 96 dB 32 kHz music >14 kHz < 0.5dB 17.6-50 kHz 60 dB 48 kHz CD quality >20 kHz < 0.5dB 26.4-50 kHz 60 dB 15.1.2.1. Earpiece The earpiece driver works in differential mode.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Parameters headset: Parameter Min BW Typ Max 20 Unit condition Hz Lower limit 4 20 kHz Upper limit Freq response -0.5 0.5 dB 20 dB FS ref ampl @997Hz DR 85 90 dB FS CCIR RL=16 ohm, gain +6dB THD+N -50 -60 dB RL=16 ohm, gain +6dB, ref signal -10 dB FS 2.4 Vpp RL= 32 ohm, ground-centered 2.0 Vpp RL= 16 ohm, ground-centered Vout R_load 14 Gain -9.1 15.1.2.3.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Parameters loudspeaker: Parameter Min BW Typ Max 20 Unit condition Hz Lower limit 4 20 kHz Upper limit Freq response -0.5 0.5 dB 20 dB FS ref ampl @997Hz DR 73 80 dB FS CCIR RL=8 ohm, gain 0dB THD+N -45 -56 dB RL=8 ohm, gain 0dB, ref signal -10 dB FS Pout fundamental wave 700 mW V_BAT=3.8V,RL= 8 ohm, 10% THD 1200 mW V_BAT=5.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 15.2. Digital 15.2.1. I2S As mentioned in the USIF part, USIF1 interface pins , on top of SPI or UART, can be configured as audio I2S port as well .The below table shows the multiplex pinout in case configured for I2S interface: USIF1-I2S pin mapping W5 USIF1_RXD I I2S1_RX CMOS 1.8V Y5 USIF1_TXD O I2S1_TX CMOS 1.8V S5 USIF1_SCLK I/O I2S1_CLK0 CMOS 1.8V U5 USIF1_CS O I2S1_WA0 CMOS 1.8V 15.2.2.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 16. Antenna(s) The antenna connection and board layout design are the most important parts in the full product design and they strongly reflect on the product’s overall performance. Read carefully and follow the requirements and the guidelines for a good and proper design. 16.1.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 remove or install the xE922-3GR module. Antennas used for this OEM module must not exceed 3dBi gain for mobile and fixed operating configurations. 16.1.1. GSM/WCDMA Antenna – PCB line Guidelines · · · · · · · · · · · · · 16.1.2. Make sure that the transmission line’s characteristic impedance is 50ohm. Keep the line on the PCB as short as possible since the antenna line loss should be less than around 0.3dB.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 16.2. WiFi/BT Antenna Requirements Antenna recommended specification: 16.3. · Frequency: 2.4-2.5GHz · Gain (peak): 2.3 dBi · VSWR : max 1.8 · Return loss : max -10 dB · Radiation : omni directional · Polarization : linear vertical · Power handling : 1W · Impedance 50 ohm GNSS Antenna Requirements The GNSS subsystem of xE922-3GR module is visualized on below block diagram.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 In case of an internal antenna configuration, it is important to keep the 50 ohm transmission line (TL) short to limit possible signal degradation between antenna and internal LNA amplifier. In case of an active external antenna, a bias circuit to feed the antenna integrated LNA is required. An inductor filter is used as RF block. Also a DC-block capacitor is required in order to keep unwanted DC voltage away from the internal RF FE devices.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 16.3.4. GNSS Antenna - PCB Line Guidelines · · · · · · · · · · 16.3.5. Ensure that the antenna line impedance is 50ohm. Keep the line on the PCB as short as possible to reduce the loss. The antenna line must have uniform characteristics, constant cross section, avoiding meanders and abrupt curves. Keep one layer of the PCB used only for the Ground plane; if possible.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 17. Mounting the module on your board 17.1. General The xE922-3GR module is designed to be compliant with a standard lead-free SMT process 17.2. Finishing & Dimensions Board finsih : ENIG (Electroless Nickel Immersion Gold) Reproduction forbidden without written authorization from Telit Communications S.p.A. - All Rights Reserved.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 17.3. Recommended foot print for the application main board 441 pads transparant top view Dimensions are in [mm].In order to easily rework the xE922-3GR it is suggested to consider that the application has a 1.5 mm placement inhibit area around the module. It is also suggested, as a common rule for an SMT component, to avoid having a mechanical part of the application in direct contact with the module.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 NOTE: In the customer application, the region under ROUTE INHIBIT (see figure above) must be clear from signal. The five horseshoe shapes, indicated in the footprint picture above, are solder resist mask openings in the surrounding GND copper fill. They provide proper GND connection for built-in RF probes on Telit’s production test jig socket.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 17.6. Recommendations for PCB Pad Dimensions (mm) It is not recommended to place via or micro-via, which are not covered by solder resist in an area of 0.3 mm around the pads unless it carries the same signal of the pad itself (see following figure). Holes in pad are allowed only for blind holes and not for through holes. Recommendations for PCB Pad Surfaces: Finish Electro-less Ni / Immersion Au Layer thickness (um) 3 –7 / 0.05 – 0.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 17.7. Solder Paste Solder Paste Lead free Sn/Ag/Cu We recommend using only “no clean” solder paste in order to avoid the cleaning of the modules after assembly. 17.7.1. Solder Reflow Recommended solder reflow profile is shown below: Reproduction forbidden without written authorization from Telit Communications S.p.A. - All Rights Reserved.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 18. Packing system The Telit xE922-3GR module is packaged on trays. The tray is JEDEC compliant, injection molded antistatic Modified Polyphenylene ether (MPPO). It has good thermal characteristics and can withstand a the standard baking temperature up to 125°C, thereby avoiding handling the modules if baking is required. The trays are rigid, thus providing more mechanical protection against transport stress.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Reproduction forbidden without written authorization from Telit Communications S.p.A. - All Rights Reserved.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 18.1. Tray Drawing Reproduction forbidden without written authorization from Telit Communications S.p.A. - All Rights Reserved.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 18.2. Moisture Sensitivity The xE922-3GR is a Moisture Sensitive Device level 3, in accordance with standard IPC/JEDEC J-STD-020. Observe all of the requirements for using this kind of components. Reproduction forbidden without written authorization from Telit Communications S.p.A. - All Rights Reserved.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 19. Safety Recommendations READ CAREFULLY Be sure that the use of this product is allowed in your country and in the environment required. The use of this product may be dangerous and must be avoided in the following areas: · Where it can interfere with other electronic devices in environments such as hospitals, airports, aircrafts, etc. · Where there is risk of explosion such as gasoline stations, oil refineries, etc.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 20. Conformity assessment issues 20.1. FCC/IC Regulatory notices 20.1.1. Modification statement Telit Communications S.p.A has not approved any changes or modifications to this device by the user. Any changes or modifications could void the user’s authority to operate the equipment. Telit Communications S.p.A n’approuve aucune modification apportée à l’appareil par l’utilisateur, quelle qu’en soit la nature.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Cet appareil est conforme aux limites d'exposition aux rayonnements de la IC pour un environnement non contrôlé. L'antenne doit être installé de façon à garder une distance minimale de 20 centimètres entre la source de rayonnements et votre corps. Gain de l'antenne doit être ci-dessous: Bande de fréquence 850 MHz band 1900 MHz band 2.4 GHz band Type d’ antenne N/A N/A Antenne dipole demi-onde Gain de l'antenne 4.37 dBi 2.11 dBi 2.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 FCC ID et l’IC du module, précédé des mots « Contient un module d'émission », du mot « Contient » ou d'une formulation similaire exprimant le même sens, comme suit: Contains FCC ID: RI7HE9223GR Contains IC: 5131A-HE9223GR CAN ICES-3 (B) / NMB-3 (B) This Class B digital apparatus complies with Canadian ICES-003. Cet appareil numérique de classe B est conforme à la norme canadienne ICES-003. 20.2.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 Hawnhekk, “Telit Communications S.P.A.”, jiddikjara li dan “xE922-3GR module” jikkonforma mal-ħtiġijiet essenzjali u ma provvedimenti oħrajn relevanti li hemm fid-Dirrettiva 1999/5/EC. “Telit Communications S.P.A.” erklærer herved at utstyret “xE922-3GR module” er i samsvar med de grunnleggende Norwegian krav og øvrige relevante krav i direktiv 1999/5/EF. Niniejszym “Telit Communications S.P.A.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 There is no restriction for the commercialization of this device in all the countries of the European Union. Final product integrating this module must be assessed against essential requirements of the 1999/5/EC (R&TTE) Directive. It should be noted that assessment does not necessarily lead to testing. Telit Communications S.p.A. recommends carrying out the following assessments: RF spectrum use (R&TTE art 3.
xE922-3GR Hardware User Guide 1VV0301272 Rev.0.8 2017-01-05 21. Document History Revision 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Date 2016-05-18 2016-06-03 2016-06-10 2016-07-19 2016-08-17 2016-09-29 2016-10-26 2017-01-05 Changes Draft Added typical power consumption table Update pwr consumption Update 60950 safety remarks Add Conformity Assessment Issues chapter Update on LGA pin AN8 Reproduction forbidden without written authorization from Telit Communications S.p.A. - All Rights Reserved.
