User's Manual

UL865-N3G Hardware User Guide

1VV0301177 Rev 2– 2015-04-20

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Mod. 0805 2011-07 Rev.2

NOTE:

According to V.24, RX/TX signal names are referred to the application side, therefore on the

UL865-N3G V2 side these signal are on the opposite direction: TXD on the application side

will be connected to the receive line (here named TXD/ rx_uart ) of the UL865-N3G V2

serial port and vice versa for RX.

NOTE:

For a minimum implementation, only the TXD and RXD lines can be connected, the other

lines can be left open provided a software flow control is implemented.

NOTE:

In order to avoid a back powering effect it is recommended to avoid having any HIGH logic

level signal applied to the digital pins of the UL865-N3G V2 when the module is powered off

or during an ON/OFF transition.

11.2. MODEM SERIAL PORT 2

The secondary serial port on the UL865-N3G V2 is a CMOS1.8V with only the RX and TX

signals. The signals of the UL865-N3G V2 serial port are:

PAD Signal I/O Function Type Comment

RXD_AUX I Auxiliary UART (RX Data from DTE) CMOS 1.8V Shared with SPI_MISO

TXD_AUX O Auxiliary UART (TX Data to DTE) CMOS 1.8V Shared with SPI_MOSI

NOTE:

Due to the shared functions, when the SPI port is used, it is not possible to use the SPI port.

NOTE:

In order to avoid a back powering effect it is recommended to avoid having any HIGH logic

level signal applied to the digital pins of the UL865-N3G V2 when the module is powered off

or during an ON_OFF transition.