UE910 3G HARDWARE USER GUIDE UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.
APPLICABILITY TABLE PRODUCTS UE910-N3G UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.
DISCLAIMER LEGAL NOTICE These Specifications are general guidelines pertaining to product selection and application and may not be appropriate for your particular project. Telit (which hereinafter shall include, its agents, licensors and affiliated companies) makes no representation as to the particular products identified in this document and makes no endorsement of any product.
HIGH RISK MATERIALS Components, units, or third-party products contained or used with the products described herein are NOT fault-tolerant and are NOT designed, manufactured, or intended for use as on-line control equipment in the following hazardous environments requiring fail-safe controls: the operation of Nuclear Facilities, Aircraft Navigation or Aircraft Communication Systems, Air Traffic Control, Life Support, or Weapons Systems (“High Risk Activities").
CONTENTS 1 Introduction 8 1.1 Scope 8 1.2 Audience 8 1.3 Contact Information, Support 8 1.4 List of acronyms 9 1.5 Text Conventions 10 1.6. Related Documents 10 2 3 Overview Pins Allocation 11 12 3.1 Pin-out 12 LGA Pads Layout 19 4 Power Supply 20 4.1 Power Supply Requirements 20 4.2 Power Consumption 21 4.
MODEM SERIAL PORT 1 (USIF0) 42 MODEM SERIAL PORT 2 (USIF1) 44 RS232 LEVEL TRANSLATION 45 General Purpose I/O 46 Using a GPIO as INPUT 47 Using a GPIO as OUTPUT 47 Indication of network service availability 48 5.7 External SIM Holder 49 5.8 ADC Converter 49 6 RF Section 50 6.1 Bands Variants 50 6.2 TX Output Power 50 6.3 RX Sensitivity 50 6.
10 Packaging 69 10.1 Tray 69 10.2 Reel 70 Carrier Tape Detail 70 Reel Detail 71 Reel Box Detail 72 10.3 Moisture sensitivity 72 11 12 13 SAFETY RECOMMANDATIONS FCC/IC Regulatory notices Document History 73 74 77 13.1 Revisions 77 UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.
1 INTRODUCTION 1.1 Scope The aim of this document is the description of some hardware solutions useful for developing a product with the Telit UE910 module. 1.2 Audience This document is intended for Telit customers, who are integrators, about to implement their applications using our UE910 modules. 1.3 Contact Information, Support For general contact, technical support services, technical questions and report documentation errors contact Telit Technical Support at: TS-EMEA@telit.
1.
1.5 Text Conventions Danger – This information MUST be followed or catastrophic equipment failure or bodily injury may occur. Caution or Warning – Alerts the user to important points about integrating the module, if these points are not followed, the module and end user equipment may fail or malfunction. Tip or Information – Provides advice and suggestions that may be useful when integrating the module. All dates are in ISO 8601 format, i.e. YYYY-MM-DD. 1.6.
2 OVERVIEW The aim of this document is the description of some hardware solutions useful for developing a product with the Telit UE910 3G module. In this document all the basic functions of a mobile phone will be taken into account; for each one of them a proper hardware solution will be suggested and eventually the wrong solutions and common errors to be avoided will be evidenced. Obviously this document cannot embrace the whole hardware solutions and products that may be designed.
3 PINS ALLOCATION 3.1 Pin-out Pin Signal I/O Function Type Comment USB HS 2.0 COMMUNICATION PORT B15 USB_D+ I/O USB differential Data (+) - C15 USB_D- I/O USB differential Data (-) - A13 VUSB I Power sense for the internal USB transceiver. - Asynchronous Serial Port (USIF0) - Prog. / Data + HW Flow Control N15 C103/TXD I Serial data input from DTE CMOS 1.8V M15 C104/RXD O Serial data output to DTE CMOS 1.8V M14 C108/DTR I Input for (DTR) from DTE CMOS 1.
A6 SIMCLK O External SIM signal – Clock 1.8 / 3V A7 SIMRST O External SIM signal – Reset 1.8 / 3V A5 SIMIO I/O External SIM signal – Data I/O 1.8 / 3V A4 SIMIN I External SIM signal – Presence (active low) A3 SIMVCC - External SIM signal – Power supply for the SIM B2 EAR+ O Analog Audio Interface (EAR+) B3 EAR- O Analog Audio Interface (EAR-) B4 MIC+ I Analog Audio Interface (MIC+) B5 MIC- I Analog Audio Interface (MIC-) CMOS 1.8 1.
L15 GPIO_09 I/O GPIO_09 CMOS 1.8V G15 GPIO_10 I/O GPIO_10 CMOS 1.8V ADC_IN1 AI Analog / Digital converter input A/D ANTENNA I/O WCDMA Antenna (50 ohm) RF ADC B1 Accepted values 0 to 1.2V DC RF SECTION K1 Miscellaneous Functions R13 HW_SHUTDOWN* I HW Unconditional Shutdown CMOS 1.8V Active low R12 ON_OFF* I Input command for power ON CMOS 1.
L2 GND - Ground Power R2 GND - Ground Power M3 GND - Ground Power N3 GND - Ground Power P3 GND - Ground Power R3 GND - Ground Power D4 GND - Ground Power M4 GND - Ground Power N4 GND - Ground Power P4 GND - Ground Power R4 GND - Ground Power N5 GND - Ground Power P5 GND - Ground Power R5 GND - Ground Power N6 GND - Ground Power P6 GND - Ground Power R6 GND - Ground Power P8 GND - Ground Power R8 GND - Ground Power
E3 RESERVED - RESERVED F3 RESERVED - RESERVED G3 RESERVED - RESERVED H3 RESERVED - RESERVED J3 RESERVED - RESERVED K3 RESERVED - RESERVED L3 RESERVED - RESERVED B4 RESERVED - RESERVED C4 RESERVED - RESERVED B5 RESERVED - RESERVED C5 RESERVED - RESERVED C6 RESERVED - RESERVED C7 RESERVED - RESERVED N7 RESERVED - RESERVED P7 RESERVED - RESERVED N8 RESERVED - RESERVED N9 RESERVED - RESERVED A10 RESERVED - RESERVED N10 RESERVED - RESERVE
G13 RESERVED - RESERVED F13 RESERVED - RESERVED B1 RESERVED - RESERVED B11 RESERVED - RESERVED B10 RESERVED - RESERVED A9 RESERVED - RESERVED A8 RESERVED - RESERVED D14 RESERVED - RESERVED A14 RESERVED - RESERVED D13 RESERVED - RESERVED E13 RESERVED - RESERVED F1 RESERVED - RESERVED R9 RESERVED - RESERVED R7 RESERVED - RESERVED P11 RESERVED - RESERVED WARNING: Reserved pins must not be connected UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.
If not used, almost all pins should be left disconnected.
LGA Pads Layout TOP VIEW A 1 B C D E F G H J K L M N P RES RES RES GND RES GND GND GND ANT GND VBATT VBATT _PA VBATT _PA R 2 GND SPK+ RES RES GND GND GND GND GND GND GND VBATT VBATT _PA VBATT _PA GND 3 SIMVC C SPK - RES RES RES RES RES RES RES RES RES GND GND GND GND 4 SIMIN MIC+ RES GND GND GND GND GND 5 SIMIO MIC - RES GND GND GND 6 SIMCL K DVI_RX RES GND GND GND 7 SIMRS T DVI_TX RES RES RES RES 8 RES DVI_CLK GPI
4 POWER SUPPLY The power supply circuitry and board layout are a very important part in the full product design and they strongly reflect on the product overall performances, hence read carefully the requirements and the guidelines that will follow for a proper design. 4.1 Power Supply Requirements The external power supply must be connected to VBATT & VBATT_PA signals and must fulfil the following requirements: Power Supply Value Nominal Supply Voltage 3.8V Normal Operating Voltage Range 3.
4.2 Power Consumption Mode Average (mA) Mode Description Switched Off 180 uA Module supplied but switched off AT+CFUN=5 1.6 Disabled TX and RX; DRX7 WCDMA Voice 170 WCDMA voice call (TX = 10dBm) WCDMA HSDPA (22dBm) 538 WCDMA data call (Cat 8, TX = 22dBm) NOTE: The electrical design for the Power supply should be made ensuring it will be capable of a peak current output of at least 1 A. UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.
4.3 General Design Rules The principal guidelines for the Power Supply Design embrace three different design steps: the electrical design the thermal design the PCB layout. Electrical Design Guidelines The electrical design of the power supply depends strongly from the power source where this power is drained.
+ 12V input Source Power Supply Design Guidelines The desired output for the power supply is 3.8V, hence due to the big difference between the input source and the desired output, a linear regulator is not suited and shall not be used. A switching power supply will be preferable because of its better efficiency. When using a switching regulator, a 500kHz or more switching frequency regulator is preferable because of its smaller inductor size and its faster transient response.
Battery Source Power Supply Design Guidelines The desired nominal output for the power supply is 3.8V and the maximum voltage allowed is 4.2V, hence a single 3.7V Li-Ion cell battery type is suited for supplying the power to the Telit UE910 module. A Bypass low ESR capacitor of adequate capacity must be provided in order to cut the current absorption peaks, a 100μF tantalum capacitor is usually suited. Make sure the low ESR capacitor (usually a tantalum one) is rated at least 10V.
Thermal Design Guidelines The thermal design for the power supply heat sink should be done with the following specifications: Average current consumption during HSDPA transmission @PWR level max : 700 mA Average current during idle: 1.8 mA Considering the very low current during idle, especially if Power Saving function is enabled, it is possible to consider from the thermal point of view that the device absorbs current significantly only during calls.
Power Supply PCB layout Guidelines As seen on the electrical design guidelines the power supply shall have a low ESR capacitor on the output to cut the current peaks on the input to protect the supply from spikes The placement of this component is crucial for the correct working of the circuitry. A misplaced component can be useless or can even decrease the power supply performances.
4.4 RTC Bypass out The VRTC pin brings out the Real Time Clock supply, which is separate from the rest of the digital part, allowing having only RTC going on when all the other parts of the device are off. To this power output a backup capacitor can be added in order to increase the RTC autonomy during power off of the battery. NO Devices must be powered from this pin.
5 DIGITAL SECTION 5.1 Logic Levels Specification ABSOLUTE MAXIMUM RATINGS – NOT FUNCTIONAL: Parameter Min Max Input level on any digital pin (CMOS 1.8) with respect to ground -0.3V 2.1V Input level on any digital pin (CMOS 1.2) with respect to ground -0.3V 1.4V Parameter Min Max Input high level 1.5V 1.9V Input low level 0V 0.35V Output high level 1.6V 1.9V Output low level 0V 0.2V Parameter Min Max Input high level 0.9V 1.3V Input low level 0V 0.
5.2 Power on To turn on the UE910 the pad ON_OFF* must be tied low for at least 5 seconds and then released. The maximum current that can be drained from the ON_OFF* pad is 0,1 mA. A simple circuit to do it is: NOTE: Don't use any pull up resistor on the ON_OFF* line, it is internally pulled up. Using pull up resistor may bring to latch up problems on the UE910 power regulator and improper power on/off of the module. The line ON_OFF* must be connected only in open collector or open drain configuration.
A flow chart showing the proper turn on procedure is displayed below: “Modem ON Proc” START N VBATT > 3.22V ? Y Y PWRMON=ON ? N ON_OFF* = LOW GO TO “HW Shutdown Unconditional” Delay = 5 sec ON_OFF* = HIGH PWRMON=ON ? N Y Delay = 1 sec GO TO “Start AT Commands”” “Modem ON Proc” END UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.
A flow chart showing the AT commands managing procedure is displayed below: “Start AT CMD” START Delay = 300 msec Enter AT AT answer in 1 sec ? N GO TO “HW Shutdown Unconditional” Y “Start AT CMD” END GO TO “Modem ON Proc.” NOTE: In order to avoid a back powering effect it is recommended to avoid having any HIGH logic level signal applied to the digital pins of the UE910 when the module is powered off or during an ON/OFF transition. UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.
For example: 1- Let's assume you need to drive the ON_OFF* pad with a totem pole output of a +3/5 V microcontroller (uP_OUT1): 2- Let's assume you need to drive the ON_OFF* pad directly with an ON/OFF button: WARNING: It is recommended to set the ON_OFF* line LOW to power on the module only after VBATT is higher than 3.22V. In case this condition it is not satisfied you could use the HW_SHUTDOWN* line to recover it and then restart the power on activity using the ON_OFF * line.
Power ON diagram: After HW_SHUTSDOWN* is released you could again use the ON_OFF* line to power on the module. UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.
5.3 Power off Turning off the device can be done in two ways: via AT command (see UE910 Software User Guide, AT#SHDN) by tying low pin ON_OFF* Either ways, the device issues a detach request to network informing that the device will not be reachable any more. To turn OFF the UE910 the pad ON_OFF* must be tied low for at least 3 seconds and then released. NOTE: To check if the device has been powered off, the hardware line PWRMON must be monitored. The device is powered off when PWRMON goes low.
The following flow chart shows the proper turn off procedure: “Modem OFF Proc.” START PWRMON=ON? N Y AT OFF Mode Key ON_OFF* = LOW Delay >= 3 sec AT#SHDN ON_OFF* = HIGH PWRMON=ON? N “Modem OFF Proc.” END Y N Looping for more than 15s? Y GO TO “HW SHUTDOWN Unconditional” UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.
5.4 Unconditional Shutdown HW_SHUTDOWN* is used to unconditionally shutdown the UE910. Whenever this signal is pulled low, the UE910 is reset. When the device is reset it stops any operation. After the release of the line, the UE910 is unconditionally shut down, without doing any detach operation from the network where it is registered. This behaviour is not a proper shut down because any WCDMA device is requested to issue a detach request on turn off.
A typical circuit is the following: For example: Let us assume you need to drive the HW_SHUTDOWN* pad with a totem pole output of a +3/5 V microcontroller (uP_OUT2): NOTE: In order to avoid a back powering effect it is recommended to avoid having any HIGH logic level signal applied to the digital pins of the UE910 when the module is powered off or during an ON/OFF transition. UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.
In the following flow chart is detailed the proper restart procedure: “HW SHUTDOWN Unconditional” START HW_SHUTDOWN* = LOW Delay = 1s Delay = 200ms Disconnect VBATT HW_SHUTDOWN* = HIGH PWRMON = ON Y N “HW SHUTDOWN Unconditional” END NOTE: Do not use any pull up resistor on the HW_SHUTDOWN* line nor any totem pole digital output. Using pull up resistor may bring to latch up problems on the UE910 power regulator and improper functioning of the module.
5.5 Communication ports USB 2.0 HS The UE910 includes one integrated universal serial bus (USB 2.0 HS) transceiver. The following table is listing the available signals: PAD Signal I/O Function Type B15 USB_D+ I/O USB differential Data (+) 3.3V C15 USB_D- I/O USB differential Data (-) 3.3V A13 VUSB AI Power sense for the internal USB transceiver. 5V NOTE Accepted range: 4.4V to 5.25V The USB_DPLUS and USB_DMINUS signals have a clock rate of 480 MHz.
USB HSIC The UE910 Module is provided by one USB HSIC interface. The USB HSIC (High Speed Inter Processor) Interface allows supporting the inter-processor communication between an application processor (AP) – the host, and the modem processor (CP) – the UE910. The following table is listing the available signals: PAD Signal I/O Function Type NOTE A12 HSIC_USB_DATA I/O USB HSIC data signal CMOS 1.2V A11 HSIC_USB_STRB I/O USB HSIC strobe signal CMOS 1.
SPI The UE910 Module is provided by one SPI interface. The SPI interface defines two handshake lines for flow control and mutual wake-up of the modem and the Application Processor: SRDY (slave ready) and MRDY (master ready). The AP has the master role, that is, it supplies the clock. The following table is listing the available signals: PAD Signal I/O Function Type NOTE D15 SPI_MOSI I SPI MOSI CMOS 1.8V Shared with TX_AUX E15 SPI_MISO O SPI MISO CMOS 1.
Serial Ports The UE910 module is provided with by 2 Asynchronous serial ports: MODEM SERIAL PORT 1 (Main) MODEM SERIAL PORT 2 (Auxiliary) Several configurations can be designed for the serial port on the OEM hardware, but the most common are: RS232 PC com port microcontroller UART @ 1.8V (Universal Asynchronous Receive Transmit) microcontroller UART @ 5V or other voltages different from 1.
The following table shows the typical input value of internal pull-up resistors for RTS, DTR and TXD input lines and in all module states: RTS DTR TXD STATE Pull up tied to ON 5K to 12K OFF Schottky diode RESET Schottky diode POWER SAVING 5K to 12K 1V8 1V8 The input line ON_OFF and HW_SHDN state can be treated as in picture below NOTE: According to V.
MODEM SERIAL PORT 2 (USIF1) The secondary serial port on the UE910 is a CMOS1.8V with only the RX and TX signals. The signals of the UE910 serial port are: PAD Signal I/O Function Type NOTE D15 TX_AUX O Auxiliary UART (TX Data to DTE) CMOS 1.8V Shared with SPI_MOSI E15 RX_AUX I Auxiliary UART (RX Data from DTE) CMOS 1.8V Shared with SPI_MISO NOTE: Due to the shared pins, when the Modem Serial port is used, it is not possible to use the SPI functions.
RS232 LEVEL TRANSLATION In order to interface the UE910 with a PC com port or a RS232 (EIA/TIA-232) application a level translator is required. This level translator must: invert the electrical signal in both directions; Change the level from 0/1.8V to +15/-15V. Actually, the RS232 UART 16450, 16550, 16650 & 16750 chipsets accept signals with lower levels on the RS232 side (EIA/TIA-562), allowing a lower voltage-multiplying ratio on the level translator.
5.6 General Purpose I/O The UE910 module is provided by a set of Configurable Digital Input / Output pins (CMOS 1.8V) Input pads can only be read; they report the digital value (high or low) present on the pad at the read time. Output pads can only be written or queried and set the value of the pad output. An alternate function pad is internally controlled by the UE910 firmware and acts depending on the function implemented.
Using a GPIO as INPUT The GPIO pads, when used as inputs, can be connected to a digital output of another device and report its status, provided this device has interface levels compatible with the 1.8V CMOS levels of the GPIO. If the digital output of the device to be connected with the GPIO input pad has interface levels different from the 1.8V CMOS, then it can be buffered with an open collector transistor with a 47K pull up to 1.8V.
Indication of network service availability The STAT_LED pin status shows information on the network service availability and Call status. The function is available as alternate function of GPIO_01 (to be enabled using the AT#GPIO=1,0,2 command). In the UE910 modules, the STAT_LED needs an external transistor to drive an external LED. Therefore, the status indicated in the following table is reversed with respect to the pin status.
5.7 External SIM Holder Please refer to the related User Guide (SIM Holder Design Guides, 80000NT10001a). 5.8 ADC Converter The UE910 is provided by one AD converter. It is able to read a voltage level in the range of 0÷1.2 volts applied on the ADC pin input, store and convert it into 10 bit word. The input line is named as ADC_IN1 and it is available on Pad B1 The following table is showing the ADC characteristics: Item Min Typical Max Unit Input Voltage range 0 - 1.
6 RF SECTION 6.1 Bands Variants The following table is listing the supported Bands: 6.2 6.3 Product Supported 3G bands UE910-N3G FDD B2, B5 TX Output Power Band Power Class FDD B2, B5 Class 3 (0.25W) RX Sensitivity Band Sensitivity FDD B2, B5 -111dBm UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.
6.4 Antenna Requirements The antenna connection and board layout design are the most important aspect in the full product design as they strongly affect the product overall performances, hence read carefully and follow the requirements and the guidelines for a proper design.
The transmission line should be designed according to the following guidelines: Ensure that the antenna line impedance is 50 ohm; Keep the antenna line on the PCB as short as possible, since the antenna line loss shall be less than 0,3 dB; Antenna line must have uniform characteristics, constant cross section; avoid meanders and abrupt curves; Keep, if possible, one layer of the PCB used only for the Ground plane; Surround (on the sides, over and under) the antenna line on PCB with Ground
PCB Guidelines in case of FCC Certification In the case FCC certification is required for an application using UE910-N3G, according to FCC KDB 996369 for modular approval requirements, the transmission line has to be similar to that implemented on UE910 interface board and described in the following chapter.
Transmission Line Measurements An HP8753E VNA (Full-2-port calibration) has been used in this measurement session. A calibrated coaxial cable has been soldered at the pad corresponding to RF output; a SMA connector has been soldered to the board in order to characterize the losses of the transmission line including the connector itself. During Return Loss / impedance measurements, the transmission line has been terminated to 50 Ω load.
Insertion Loss of G-CPW line plus SMA connector is shown below: UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.
Antenna Installation Guidelines Install the antenna in a place covered by the WCDMA signal. If the device antenna is located farther than 20cm from the human body and there are no co-located transmitter then the Telit FCC/IC approvals can be re-used by the end product. If the device antenna is located closer than 20cm from the human body or there are co-located transmitter then the additional FCC/IC testing may be required for the end product (Telit FCC/IC approvals cannot be reused).
7 AUDIO SECTION 7.1 Overview The UE910 is provided by two main Audio interfaces: Analog Audio Path Digital Audio Path NOTE: The two Paths could not be used in parallel; If the Analog Voice lines are selected, the DVI interface is disabled and Vice versa. 7.2 Analog Voice Interface The Base Band Chip of the UE910 provides one differential input for audio to be transmitted (Uplink) and a balanced BTL output for audio to be received (downlink).
MIC connection The bias for the microphone has to be as clean as possible; the first connection (single ended) is preferable since the Vmic noise and ground noise are fed into the input as common mode and then rejected. This sounds strange; usually the connection to use in order to reject the common mode is the balanced one.
If a "balanced way" is anyway desired, much more care has to be taken to Vmic noise and ground noise; also the 33pF-100Ohm-33pF RF-filter has to be doubled (one each wire). NOTE: Since the J-FET transistor inside the microphone acts as RF-detector-amplifier, ask vendor for a microphone with anti-EMI capacitor (usually a 33pF or a 10pF capacitor placed across the output terminals inside the case). UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.
LINE IN Connection If the audio source is not a mike but a different device, the following connections can be done. Place 100nF capacitor in series with both inputs, so the DC current is blocked. Place the 33pF-100Ohm-33pF RF-filter, in order to prevent some EMI field to get into the high impedance high gain MIC inputs. Since the input is differential, the common mode voltage noise between the two (different) ground is rejected, provided that both MIC+ & MIC- are connected directly onto the source.
EAR Connection The audio output of the UE910 is balanced, this is helpful to double the level and to reject common mode (click and pop are common mode and therefore rejected). These outputs can drive directly a small loudspeaker with electrical impedance not lower than 16 Ohm. NOTE: In order to get the maximum audio level at a given output voltage level (dBspl/Vrms), the following breaking through procedure can be used.
7.3 Digital Voice Interface The UE910 Module is provided by one DVI digital voice interface. The Signals are available on the following Pads: PAD Signal I/O Function B9 DVI_WA0 I/O Digital Voice Interface (Word Alignment / LRCLK) B6 DVI_RX I Digital Voice Interface (RX) B7 DVI_TX O Digital Voice Interface (TX) B8 DVI_CLK I/O Digital Voice Interface (BCLK) CODEC Examples Please refer to the Digital Audio Application note. UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.
8 MECHANICAL DESIGN 8.1 Drawing PIN B1 Lead Free Alloy: Surface Finishing Ni/Au for all solder pads Dimensions in mm UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.
9 APPLICATION DESIGN The UE910 modules have been designed in order to be compliant with a standard lead-free SMT process. 9.1 Footprint TOP VIEW In order to easily rework the UE910 is suggested to consider on the application a 1.5 mm placement inhibit area around the module. It is also suggested, as common rule for an SMT component, to avoid having a mechanical part of the application in direct contact with the module.
9.2 PCB pad design Non solder mask defined (NSMD) type is recommended for the solder pads on the PCB. Copper Pad Solder Mask PCB SMD (Solder Mask Defined) 9.3 NSMD (Non Solder Mask Defined) PCB pad dimensions The recommendation for the PCB pads dimensions are described in the following image (dimensions in mm) Solder resist openings UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.
It is not recommended to place via or micro-via not covered by solder resist in an area of 0,3 mm around the pads unless it carries the same signal of the pad itself (see following figure). Inhibit area for micro-via Holes in pad are allowed only for blind holes and not for through holes. Recommendations for PCB pad surfaces: Finish Layer Thickness (um) Properties Electro-less Ni / Immersion Au 3 –7 / 0.05 – 0.
9.4 Stencil Stencil’s apertures layout can be the same of the recommended footprint (1:1), we suggest a thickness of stencil foil ≥ 120 µm. 9.5 Solder paste Item Lead Free Solder Paste Sn/Ag/Cu We recommend using only “no clean” solder paste in order to avoid the cleaning of the modules after assembly. 9.6 Solder reflow Recommended solder reflow profile: UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.
Profile Feature Pb-Free Assembly Average ramp-up rate (TL to TP) 3°C/second max Preheat – Temperature Min (Tsmin) – Temperature Max (Tsmax) – Time (min to max) (ts) 150°C 200°C 60-180 seconds Tsmax to TL – Ramp-up Rate 3°C/second max Time maintained above: – Temperature (TL) – Time (tL) 217°C 60-150 seconds Peak Temperature (Tp) 245 +0/-5°C Time within 5°C of actual Peak Temperature (tp) 10-30 seconds Ramp-down Rate 6°C/second max. Time 25°C to Peak Temperature 8 minutes max.
10 PACKAGING 10.1 Tray The UE910 modules are packaged on trays of 36 pieces each. These trays can be used in SMT processes for pick & place handling. UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.
10.2 Reel The UE910 can be packaged on reels of 200 pieces each. See figure for module positioning into the carrier. Carrier Tape Detail UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.
Reel Detail UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.
Reel Box Detail 10.3 Moisture sensitivity The UE910 is a Moisture Sensitive Device level 3, in according with standard IPC/JEDEC J-STD-020, take care all the relatives requirements for using this kind of components. Moreover, the customer has to take care of the following conditions: a) Calculated shelf life in sealed bag: 12 months at <40°C and <90% relative humidity (RH). b) Environmental condition during the production: 30°C / 60% RH according to IPC/JEDEC J-STD033A paragraph 5.
11 SAFETY RECOMMANDATIONS READ CAREFULLY Be sure the use of this product is allowed in the country and in the environment required.
12 FCC/IC REGULATORY NOTICES Modification statement Telit has not approved any changes or modifications to this device by the user. Any changes or modifications could void the user’s authority to operate the equipment. Telit n’approuve aucune modification apportée à l’appareil par l’utilisateur, quelle qu’en soit la nature. Tout changement ou modification peuvent annuler le droit d’utilisation de l’appareil par l’utilisateur.
Cet appareil est conforme aux limites d'exposition aux rayonnements de la IC pour un environnement non contrôlé. L'antenne doit être installé de façon à garder une distance minimale de 20 centimètres entre la source de rayonnements et votre corps. Gain de l'antenne doit être ci-dessous: Bande de fréquence Gain Band II (1900 MHz) 9.01 dBi Band V (850 MHz) 7.76 dBd L'émetteur ne doit pas être colocalisé ni fonctionner conjointement avec à autre antenne ou autre émetteur.
L'appareil hôte doit être étiqueté comme il faut pour permettre l'identification des modules qui s'y trouvent. L'étiquette de certification du module donné doit être posée sur l'appareil hôte à un endroit bien en vue en tout temps.
13 DOCUMENT HISTORY 13.1 Revisions Revision Date Changes 0 2014-10-01 Preliminary Version 1 2015-01-08 Updated document format 2 2015-03-31 Added RX Sensitivity Added Third Party Rights Added FCC/IC Regulatory Notices Safety Recommendations Updated Tray Packaging Updated Chapter 4.2 3 2015-04-17 Updated Chapter 12 UE910 3G HARDWARE USER GUIDE 1vv0301171 Rev.
