UE866 HARDWARE USER GUIDE UE866 HARDWARE USER GUIDE 1vv0301157 Rev.
APPLICABILITY TABLE PRODUCTS UE866-N3G UE866 HARDWARE USER GUIDE 1vv0301157 Rev.
DISCLAIMER LEGAL NOTICE These Specifications are general guidelines pertaining to product selection and application and may not be appropriate for your particular project. Telit (which hereinafter shall include, its agents, licensors and affiliated companies) makes no representation as to the particular products identified in this document and makes no endorsement of any product.
HIGH RISK MATERIALS Components, units, or third-party products contained or used with the products described herein are NOT fault-tolerant and are NOT designed, manufactured, or intended for use as on-line control equipment in the following hazardous environments requiring fail-safe controls: the operation of Nuclear Facilities, Aircraft Navigation or Aircraft Communication Systems, Air Traffic Control, Life Support, or Weapons Systems (“High Risk Activities").
CONTENTS 1 Introduction 8 1.1 Scope 8 1.2 Audience 8 1.3 Contact Information, Support 8 1.4 List of acronyms 9 1.5 Text Conventions 10 1.6. Related Documents 10 2 3 Overview Pins Allocation 11 12 3.1 Pin-out 12 LGA Pads Layout 16 4 Power Supply 17 4.1 Power Supply Requirements 17 4.2 Power Consumption 18 4.
MODEM SERIAL PORT 2 (USIF1) 37 RS232 LEVEL TRANSLATION 38 General Purpose I/O 39 Using a GPIO as INPUT 40 Using a GPIO as OUTPUT 40 Indication of network service availability 41 SIMIN Detection 42 5.7 External SIM Holder 42 5.8 ADC Converter 43 5.9 DAC Converter 44 Enabling DAC 44 LOW Pass filter Example 45 5.6 6 RF Section 46 6.1 Bands Variants 46 6.2 TX Output Power 46 6.3 RX Sensitivity 46 6.
10.2 Moisture sensitivity 62 11 12 13 SAFETY RECOMMANDATIONS FCC/IC Regulatory notices Document History 63 64 67 13.1 Revisions 67 UE866 HARDWARE USER GUIDE 1vv0301157 Rev.
1 INTRODUCTION 1.1 Scope The aim of this document is the description of some hardware solutions useful for developing a product with the Telit UE866 module. 1.2 Audience This document is intended for Telit customers, who are integrators, about to implement their applications using our UE866 modules. 1.3 Contact Information, Support For general contact, technical support services, technical questions and report documentation errors contact Telit Technical Support at: TS-EMEA@telit.
1.
1.5 Text Conventions Danger – This information MUST be followed or catastrophic equipment failure or bodily injury may occur. Caution or Warning – Alerts the user to important points about integrating the module, if these points are not followed, the module and end user equipment may fail or malfunction. Tip or Information – Provides advice and suggestions that may be useful when integrating the module. All dates are in ISO 8601 format, i.e. YYYY-MM-DD. 1.6.
2 OVERVIEW The aim of this document is the description of some hardware solutions useful for developing a product with the Telit UE866 3G module. In this document all the basic functions of a mobile phone will be taken into account; for each one of them a proper hardware solution will be suggested and eventually the wrong solutions and common errors to be avoided will be evidenced. Obviously this document cannot embrace the whole hardware solutions and products that may be designed.
3 PINS ALLOCATION 3.1 Pin-out Pin Signal I/O Function Type Comment USB HS 2.0 COMMUNICATION PORT E5 USB_D+ I/O USB differential Data (+) - E6 USB_D- I/O USB differential Data (-) - D4 USB_VBUS AI Power sense for the internal USB transceiver. - Asynchronous Serial Port (USIF0) - Prog. / Data + HW Flow Control B2 C109/DCD O Output for Data carrier detect signal (DCD) to DTE CMOS 1.8V B3 C125/RING O Output for Ring indicator signal (RI) to DTE CMOS 1.
/ Digital Audio Interface (WA0) C6 GPIO_02 / JDR / DVI_RX I/O GPIO02 I/O pin / Jammer Detect Report / Digital Audio Interface (RX) CMOS 1.8V D6 GPIO_03 / DVI_TX I/O GPIO03 GPIO I/O pin / Digital Audio Interface (TX) CMOS 1.8V D5 GPIO_04 / DVI_CLK I/O GPIO04 Configurable GPIO Digital Audio Interface (CLK) CMOS 1.8V B5 GPIO_05 I/O GPIO05 Configurable GPIO CMOS 1.8V B4 GPIO_06 I/O GPIO06 Configurable GPIO / ALARM CMOS 1.8V C4 GPIO_07 I/O GPIO07 Configurable GPIO / STATLED CMOS 1.
G3 GND - Ground Power F6 GND - Ground Power A8 GND - Ground Power G8 GND - Ground Power A11 GND - Ground Power G11 GND - Ground Power D3 RESERVED - RESERVED G5 RESERVED - RESERVED B6 RESERVED - RESERVED D7 RESERVED - RESERVED E7 RESERVED - RESERVED F7 RESERVED - RESERVED G7 RESERVED - RESERVED B8 RESERVED - RESERVED C8 RESERVED - RESERVED D8 RESERVED - RESERVED E8 RESERVED - RESERVED F8 RESERVED - RESERVED A9 RESERVED - RESERVE
WARNING: Reserved pins must not be connected If not used, almost all pins should be left disconnected.
LGA Pads Layout TOP VIEW A B C D E F G 1 C105/RTS C106/CTS TX AUX GND VBATT_PA GND GND 2 C108/DTR C109/DCD RX AUX GND VBATT GND ANT 3 C107/DSR C125/RING GND RFU GND GND GND 4 C103/TXD GPIO_06 GPIO_07 USB_VBUS DAC_OUT ADC_IN1 RESET* 5 C104/RXD GPIO_05 GPIO_01 GPIO_04 USB_D+ VRTC RESERVED 6 SIMIO RESERVED GPIO_02 GPIO_03 USB_D- GND VAUX/PWR MON 7 SIMCLK SIMRST SIMVCC RESERVED RESERVED RESERVED RESERVED 8 GND RESERVED RFU RFU RFU RFU GND 9
4 POWER SUPPLY The power supply circuitry and board layout are a very important part in the full product design and they strongly reflect on the product overall performances, hence read carefully the requirements and the guidelines that will follow for a proper design. 4.1 Power Supply Requirements The external power supply must be connected to VBATT & VBATT_PA signals and must fulfil the following requirements: Power Supply Value Nominal Supply Voltage 3.8V Normal Operating Voltage Range 3.
4.2 Power Consumption Mode Average (mA) AT+CFUN=5 1.6 mA Mode Description Disabled TX and RX; DRX7 WCDMA Voice 175 WCDMA voice call (TX = 10dBm) WCDMA HSDPA (22dBm) 490 WCDMA data call (Cat 8, TX = 22dBm) NOTE: The electrical design for the Power supply should be made ensuring it will be capable of a peak current output of at least 1 A. UE866 HARDWARE USER GUIDE 1vv0301157 Rev.
4.3 General Design Rules The principal guidelines for the Power Supply Design embrace three different design steps: the electrical design the thermal design the PCB layout. Electrical Design Guidelines The electrical design of the power supply depends strongly from the power source where this power is drained.
+ 12V input Source Power Supply Design Guidelines The desired output for the power supply is 3.8V, hence due to the big difference between the input source and the desired output, a linear regulator is not suited and shall not be used. A switching power supply will be preferable because of its better efficiency. When using a switching regulator, a 500kHz or more switching frequency regulator is preferable because of its smaller inductor size and its faster transient response.
Battery Source Power Supply Design Guidelines The desired nominal output for the power supply is 3.8V and the maximum voltage allowed is 4.2V, hence a single 3.7V Li-Ion cell battery type is suited for supplying the power to the Telit UE866 module. A Bypass low ESR capacitor of adequate capacity must be provided in order to cut the current absorption peaks, a 100μF tantalum capacitor is usually suited. Make sure the low ESR capacitor (usually a tantalum one) is rated at least 10V.
Thermal Design Guidelines The thermal design for the power supply heat sink should be done with the following specifications: Average current consumption during HSDPA transmission @PWR level max : 700 mA Average current during idle: 1.8 mA Considering the very low current during idle, especially if Power Saving function is enabled, it is possible to consider from the thermal point of view that the device absorbs current significantly only during calls.
Power Supply PCB layout Guidelines As seen on the electrical design guidelines the power supply shall have a low ESR capacitor on the output to cut the current peaks on the input to protect the supply from spikes The placement of this component is crucial for the correct working of the circuitry. A misplaced component can be useless or can even decrease the power supply performances.
4.4 RTC Bypass out The VRTC pin brings out the Real Time Clock supply, which is separate from the rest of the digital part, allowing having only RTC going on when all the other parts of the device are off. To this power output a backup capacitor can be added in order to increase the RTC autonomy during power off of the battery. NO Devices must be powered from this pin.
5 DIGITAL SECTION 5.1 Logic Levels Specification ABSOLUTE MAXIMUM RATINGS – NOT FUNCTIONAL: Parameter Min Max Input level on any digital pin (CMOS 1.8) with respect to ground -0.3V 2.1V Parameter Min Max Input high level 1.5V 1.9V Input low level 0V 0.35V Output high level 1.6V 1.9V Output low level 0V 0.2V OPERATING RANGE - INTERFACE LEVELS (1.8V CMOS): CURRENT CHARACTERISTICS: Parameter AVG Output Current 1mA Input Current 1uA UE866 HARDWARE USER GUIDE 1vv0301157 Rev.
5.2 Power on The UE866 will automatically power on itself when VBATT & VBATT_PA are applied to the module. VAUX / PWRMON pin will be at the high logic level and the module can be considered fully operating after 5 seconds. The following flow chart shows the proper turn on procedure: “Modem ON Proc” START N PWR Supply ON & > 3.
A flow chart showing the AT commands managing procedure is displayed below: “Start AT CMD” START Delay = 300 msec Enter AT AT answer in 1 sec ? N Disconnect PWR Supply Y “Start AT CMD” END GO TO “Modem ON Proc.” NOTE: In order to avoid a back powering effect it is recommended to avoid having any HIGH logic level signal applied to the digital pins of the UE866 when the module is powered off or during an ON/OFF transition. UE866 HARDWARE USER GUIDE 1vv0301157 Rev.
WARNING: It is recommended to power on the module only after VBATT is higher than 3.22V. The maximum rump up time for VBATT is 21mS. In case this condition it is not satisfied you could use the HW_SHUTDOWN* line to recover it. An example of this is described in the following diagram: After RESET* is released the module will automatically power on itself. UE866 HARDWARE USER GUIDE 1vv0301157 Rev.
5.3 Power off The following flowchart shows the proper Turn-off procedure: “Modem OFF Proc” AT#SYSHALT 10s Timeout Disconnect PWR Supply Delay 1.5s “Modem ON Proc.” In order to avoid a back powering effect it is recommended to avoid having any HIGH logic level signal applied to the digital pins of the UE866 when the module is powered off or during an ON/OFF transition. UE866 HARDWARE USER GUIDE 1vv0301157 Rev.
5.4 Reset To unconditionally reboot the UE866, the pad RESET* must be tied low for at least 200 milliseconds and then released. The maximum current that can be drained from the RESET* pad is 0,15 mA. The hardware unconditional Restart must not be used during normal operation of the device since it does not detach the device from the network. It shall be kept as an emergency exit procedure to be done in the rare case that the device gets stuck waiting for some network or SIM responses.
A typical circuit is the following: NOTE: In order to avoid a back powering effect it is recommended to avoid having any HIGH logic level signal applied to the digital pins of the UE866 when the module is powered off or during an ON/OFF transition. UE866 HARDWARE USER GUIDE 1vv0301157 Rev.
In the following flow chart is detailed the proper restart procedure: Modem RESET Proc. RESET* = LOW Delay = 200ms RESET* = HIGH Delay = 1s Start At CMD NOTE: Do not use any pull up resistor on the HW_SHUTDOWN* line nor any totem pole digital output. Using pull up resistor may bring to latch up problems on the UE866 power regulator and improper functioning of the module.
5.5 Communication ports USB 2.0 HS The UE866 includes one integrated universal serial bus (USB 2.0 HS) transceiver. The following table is listing the available signals: PAD Signal I/O Function Type E5 USB_D+ I/O USB differential Data (+) 3.3V E6 USB_D- I/O USB differential Data (-) 3.3V D4 VUSB AI Power sense for the internal USB transceiver. 5V NOTE Accepted range: 4.4V to 5.25V The USB_DPLUS and USB_DMINUS signals have a clock rate of 480 MHz.
SPI The UE866 Module is provided by one SPI interface. The SPI interface defines two handshake lines for flow control and mutual wake-up of the modem and the Application Processor: SRDY (slave ready) and MRDY (master ready). The AP has the master role, that is, it supplies the clock. The following table is listing the available signals: PAD Signal I/O Function Type NOTE C1 SPI_MOSI I SPI MOSI CMOS 1.8V Shared with TX_AUX C2 SPI_MISO O SPI MISO CMOS 1.
Serial Ports The UE866 module is provided with by 2 Asynchronous serial ports: MODEM SERIAL PORT 1 (Main) MODEM SERIAL PORT 2 (Auxiliary) Several configurations can be designed for the serial port on the OEM hardware, but the most common are: RS232 PC com port microcontroller UART @ 1.8V (Universal Asynchronous Receive Transmit) microcontroller UART @ 5V or other voltages different from 1.
The following table shows the typical input value of internal pull-up resistors for RTS, DTR and TXD input lines and in all module states: RTS DTR TXD STATE Pull up tied to ON 5K to 12K OFF Schottky diode RESET Schottky diode POWER SAVING 5K to 12K 1V8 1V8 The input line ON_OFF and HW_SHDN state can be treated as in picture below NOTE: According to V.
MODEM SERIAL PORT 2 (USIF1) The secondary serial port on the UE866 is a CMOS1.8V with only the RX and TX signals. The signals of the UE866 serial port are: PAD Signal I/O Function Type NOTE C1 TX_AUX O Auxiliary UART (TX Data to DTE) CMOS 1.8V Shared with SPI_MOSI C2 RX_AUX I Auxiliary UART (RX Data from DTE) CMOS 1.8V Shared with SPI_MISO NOTE: Due to the shared pins, when the Modem Serial port is used, it is not possible to use the SPI functions.
RS232 LEVEL TRANSLATION In order to interface the UE866 with a PC com port or a RS232 (EIA/TIA-232) application a level translator is required. This level translator must: invert the electrical signal in both directions; Change the level from 0/1.8V to +15/-15V. Actually, the RS232 UART 16450, 16550, 16650 & 16750 chipsets accept signals with lower levels on the RS232 side (EIA/TIA-562), allowing a lower voltage-multiplying ratio on the level translator.
5.6 General Purpose I/O The UE866 module is provided by a set of Configurable Digital Input / Output pins (CMOS 1.8V) Input pads can only be read; they report the digital value (high or low) present on the pad at the read time. Output pads can only be written or queried and set the value of the pad output. An alternate function pad is internally controlled by the UE866 firmware and acts depending on the function implemented.
Also the UART’s control flow pins can be usable as GPIO: PAD Signal I/O Input/output Default ON_OFF current State state Reset State NOTE B2 GPO_A O 1uA/1mA INPUT 0 0 Alternate function C109/DCD B3 GPO_B O 1uA/1mA INPUT 0 0 Alternate function C125/RING A3 GPO_C O 1uA/1mA INPUT 0 0 Alternate function C107/DSR A2 GPI_E I 1uA/1mA INPUT 0 0 Alternate function C108/DTR A1 GPI_F I 1uA/1mA INPUT 0 0 Alternate function C105/RTS B1 GPO_D O 1uA/1mA INPUT 0 0 Altern
Indication of network service availability The STAT_LED pin status shows information on the network service availability and Call status. The function is available as alternate function of GPIO_07 (to be enabled using the AT#GPIO=7,0,2 command). In the UE866 modules, the STAT_LED needs an external transistor to drive an external LED. Therefore, the status indicated in the following table is reversed with respect to the pin status.
SIMIN Detection All the GPIO pins can be used as SIM DETECT input. The AT Command used to enable the function is: AT#SIMINCFG Use the AT command AT#SIMDET=2 to enable the SIMIN detection Use the AT command AT&W0 and AT&P0 to store the SIMIN detection in the common profile. NOTE: Don’t use the SIM IN function on the same pin where the GPIO function is enabled and vice versa! 5.7 External SIM Holder Please refer to the related User Guide (SIM Holder Design Guides, 80000NT10001a).
5.8 ADC Converter The UE866 is provided by one AD converter. It is able to read a voltage level in the range of 0÷1.2 volts applied on the ADC pin input, store and convert it into 10 bit word. The input line is named as ADC_IN1 and it is available on Pad F4 The following table is showing the ADC characteristics: Item Min Typical Max Unit Input Voltage range 0 - 1.
5.9 DAC Converter The UE866 provides a Digital to Analog Converter. The signal (named DAC_OUT) is available on pin E4 of the UE866. The on board DAC is a 10 bit converter, able to generate an analogue value based on a specific input in the range from 0 up to 1023. However, an external low-pass filter is necessary The following table is showing the ADC characteristics: Item Min Max Unit Voltage range (filtered) 0 1.
LOW Pass filter Example UE866 HARDWARE USER GUIDE 1vv0301157 Rev.
6 RF SECTION 6.1 Bands Variants The following table is listing the supported Bands: 6.2 6.3 Product Supported 3G bands UE866-N3G FDD B2, B5 TX Output Power Band Power Class FDD B2, B5 Class 3 (0.25W) RX Sensitivity Band Sensitivity FDD B2, B5 -110dBm UE866 HARDWARE USER GUIDE 1vv0301157 Rev.
6.4 Antenna Requirements The antenna connection and board layout design are the most important aspect in the full product design as they strongly affect the product overall performances, hence read carefully and follow the requirements and the guidelines for a proper design.
The transmission line should be designed according to the following guidelines: Ensure that the antenna line impedance is 50 ohm; Keep the antenna line on the PCB as short as possible, since the antenna line loss shall be less than 0,3 dB; Antenna line must have uniform characteristics, constant cross section; avoid meanders and abrupt curves; Keep, if possible, one layer of the PCB used only for the Ground plane; Surround (on the sides, over and under) the antenna line on PCB with Ground
PCB Guidelines in case of FCC Certification In the case FCC certification is required for an application using UE866-N3G, according to FCC KDB 996369 for modular approval requirements, the transmission line has to be similar to that implemented on UE866 interface board and described in the following chapter.
Transmission Line Measurements An HP8753E VNA (Full-2-port calibration) has been used in this measurement session. A calibrated coaxial cable has been soldered at the pad corresponding to RF output; a SMA connector has been soldered to the board in order to characterize the losses of the transmission line including the connector itself. During Return Loss / impedance measurements, the transmission line has been terminated to 50 Ω load.
Insertion Loss of G-CPW line plus SMA connector is shown below: UE866 HARDWARE USER GUIDE 1vv0301157 Rev.
Antenna Installation Guidelines Install the antenna in a place covered by the WCDMA signal. If the device antenna is located farther than 20cm from the human body and there are no co-located transmitter then the Telit FCC/IC approvals can be re-used by the end product. If the device antenna is located closer than 20cm from the human body or there are co-located transmitter then the additional FCC/IC testing may be required for the end product (Telit FCC/IC approvals cannot be reused).
7 AUDIO SECTION 7.1 Overview The UE866 is provided by one Digital Audio Interface. 7.2 Digital Voice Interface The UE866 Module is provided by one DVI digital voice interface.
8 MECHANICAL DESIGN 8.1 Drawing Pin A1 Lead-free Alloy: Surface finishing Ni/Au for all solder pads Dimensions in mm UE866 HARDWARE USER GUIDE 1vv0301157 Rev.
9 APPLICATION DESIGN The UE866 modules have been designed in order to be compliant with a standard lead-free SMT process. 9.1 Footprint In order to easily rework the UE866 is suggested to consider on the application a 1.5 mm placement inhibit area around the module. It is also suggested, as common rule for an SMT component, to avoid having a mechanical part of the application in direct contact with the module.
9.2 PCB pad design Non solder mask defined (NSMD) type is recommended for the solder pads on the PCB. Copper Pad Solder Mask PCB SMD (Solder Mask Defined) 9.3 NSMD (Non Solder Mask Defined) PCB pad dimensions The recommendation for the PCB pads dimensions are described in the following image (dimensions in mm) Solder resist openings UE866 HARDWARE USER GUIDE 1vv0301157 Rev.
It is not recommended to place via or micro-via not covered by solder resist in an area of 0,3 mm around the pads unless it carries the same signal of the pad itself (see following figure). Inhibit area for micro-via Holes in pad are allowed only for blind holes and not for through holes. Recommendations for PCB pad surfaces: Finish Layer Thickness (um) Properties Electro-less Ni / Immersion Au 3 –7 / 0.05 – 0.
9.4 Stencil Stencil’s apertures layout can be the same of the recommended footprint (1:1), we suggest a thickness of stencil foil ≥ 120 µm. 9.5 Solder paste Item Lead Free Solder Paste Sn/Ag/Cu We recommend using only “no clean” solder paste in order to avoid the cleaning of the modules after assembly. 9.6 Solder reflow Recommended solder reflow profile: UE866 HARDWARE USER GUIDE 1vv0301157 Rev.
Profile Feature Pb-Free Assembly Average ramp-up rate (TL to TP) 3°C/second max Preheat – Temperature Min (Tsmin) – Temperature Max (Tsmax) – Time (min to max) (ts) 150°C 200°C 60-180 seconds Tsmax to TL – Ramp-up Rate 3°C/second max Time maintained above: – Temperature (TL) – Time (tL) 217°C 60-150 seconds Peak Temperature (Tp) 245 +0/-5°C Time within 5°C of actual Peak Temperature (tp) 10-30 seconds Ramp-down Rate 6°C/second max. Time 25°C to Peak Temperature 8 minutes max.
10 PACKAGING 10.1 Tray The UE866 modules are packaged on trays of 20 pieces each. These trays can be used in SMT processes for pick & place handling. UE866 HARDWARE USER GUIDE 1vv0301157 Rev.
UE866 HARDWARE USER GUIDE 1vv0301157 Rev.
10.2 Moisture sensitivity The UE866 is a Moisture Sensitive Device level 3, in according with standard IPC/JEDEC J-STD-020, take care all the relatives requirements for using this kind of components. Moreover, the customer has to take care of the following conditions: a) Calculated shelf life in sealed bag: 12 months at <40°C and <90% relative humidity (RH). b) Environmental condition during the production: 30°C / 60% RH according to IPC/JEDEC J-STD033A paragraph 5.
11 SAFETY RECOMMANDATIONS READ CAREFULLY Be sure the use of this product is allowed in the country and in the environment required.
12 FCC/IC REGULATORY NOTICES Modification statement Telit has not approved any changes or modifications to this device by the user. Any changes or modifications could void the user’s authority to operate the equipment. Telit n’approuve aucune modification apportée à l’appareil par l’utilisateur, quelle qu’en soit la nature. Tout changement ou modification peuvent annuler le droit d’utilisation de l’appareil par l’utilisateur.
Cet appareil est conforme aux limites d'exposition aux rayonnements de la IC pour un environnement non contrôlé. L'antenne doit être installé de façon à garder une distance minimale de 20 centimètres entre la source de rayonnements et votre corps. Gain de l'antenne doit être ci-dessous: Bande de fréquence Gain Band II (1900 MHz) 9.01 dBi Band V (850 MHz) 7.76 dBd L'émetteur ne doit pas être colocalisé ni fonctionner conjointement avec à autre antenne ou autre émetteur.
L'appareil hôte doit être étiqueté comme il faut pour permettre l'identification des modules qui s'y trouvent. L'étiquette de certification du module donné doit être posée sur l'appareil hôte à un endroit bien en vue en tout temps.
13 DOCUMENT HISTORY 13.1 Revisions Revision Date Changes 0 2014-09-19 Preliminary Version 1 2014-09-30 Updated Chapter 4.1; removed chapter 1.4 2 2014-10-03 Updated Chapter 4.1 3 2014-10-09 Updated Chapter 2, 3, 8.5 4 2015-01-08 Updated Document Template, Packaging, Flowcharts 5 2015-01-13 Added Safety Recommendations Added FCC / IC Regulatory notices Updated Chapter 2 6 2015-03-30 Updated chapters 4.2, 4.4, 4.5, 5.2, 5.
