User's Guide

ATOP3.5G Product Description
80447ST10636A rev.10 – 2015-03-03
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8.6 Smartcard and JCOP operating system
Remark: This paragraph applies only to OM12030/1X0 (with X as defined in Section 5).
For telematics and other high value applications, it is paramount to protect against data tampering,
loading of unauthorized applications, ID stealing, as well as to protect end-user privacy. For this, a
secured component such as a smartcard is required as a root of trust.
In ATOP 3.5G this is achieved by a SmartMX co-processor with the following features:
 Latest built-in security features to avoid power (SPA/DPA), timing and fault attacks
 20 KB EEPROM
o Typical 500000 cycles endurance and minimum 20 years retention time
 6144 Bytes RAM
 Secure cryptographic processor
o High-performance secured Public Key Infrastructure (PKI) with RSA up to 2048,
ECC GF(p) up to 320 bits
o AES up to 256 bits and triple-DES
For portability and to allow multiple secure application cardlets to run in complete isolation, ATOP
3.5G offers a Java Card Open Platform operating system (JCOP) v2.4.2 based on independent,
third-party specifications, that is, by Sun Microsystems, the Global Platform consortium, the
International Organization for Standards (ISO), EMV (Europay, MasterCard and VISA) and others.
The SmartMX family was designed to service high volume, single-application and multi-application
markets such as eGovernment, Smart Passport, banking/finance, mobile communications, public
transportation, pay TV, conditional access, network access and digital rights management, thus
ensuring applications running on ATOP 3.5G can rely on the highest level of security available.
For more information, contact the Telit Technical Support Center (TTSC).
8.7 Debugging versus software security
While debug capabilities are a must, the observability, test, and control capabilities they provide
can also be used for device tampering. ATOP 3.5G offers debug capabilities and security features
that ensure that only signed software is executed. It is up to the customer to enable this.
Unlocking is not possible.
For debug, the following features are present:
 LPC1768 MCU
o CPU debug via JTAG or Serial Wire Debug interface;
o Unique Serial Number;
o Core Read Protection with multiple levels.
For security, the following features are present and can protect against unauthorized debug, code
tampering and insertion:
 Observability
o JTAG access locked down until authentication is performed;
o Secure debug with authentication.
 Code authentication and integrity
o Code is signed with Public Key cryptography to ensure authentication and
checked at boot.