User's Guide

ATOP3.5G Product Description
80447ST10636A rev.10 – 2015-03-03
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Mod. 0808 2011-07 Rev.2
The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring
PLL values and/or altering the CPU clock divider value. This allows a trade-off of power versus
processing speed based on application requirements. In addition, Peripheral Power Control
allows shutting down the clocks to individual on-chip peripherals, allowing fine-tuning of power
consumption by eliminating all dynamic power use in any peripherals that are not required for the
application. Each of the peripherals has its own clock divider which provides even better power
control.
An integrated PMU (Power Management Unit) automatically adjusts internal regulators to
minimize power consumption during Sleep mode, Deep sleep mode, Power-down mode and
Deep power-down mode.
The LPC1768 also implements a separate power domain to allow turning off power to the bulk of
the device while maintaining operation of the RTC and a small set of registers for storing data
during any of the Power-down modes.
Sleep mode: When Sleep mode is entered, the clock to the core is stopped. Resumption from the
Sleep mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a Reset or interrupt occurs.
Peripheral functions continue operation during Sleep mode and may generate interrupts to cause
the processor to resume execution. Sleep mode eliminates dynamic power used by the
processor itself, memory systems and related controllers and internal buses.
Deep sleep mode: In Deep sleep mode, the oscillator is shut down and the chip receives no
internal clocks. The processor state and registers, peripheral registers and internal SRAM values
are preserved throughout Deep sleep mode and the logic levels of chip pins remain static. The
output of the IRC is disabled but the IRC is not powered down for a fast wake-up later.
The RTC oscillator is not stopped because the RTC interrupts may be used as the wake-up
source. The PLL is automatically turned off and disconnected.
The Deep sleep mode can be terminated and normal operation resumed by either a reset or
certain specific interrupts that are able to function without clocks. Since all dynamic operation of
the chip is suspended, this mode reduces chip power consumption to a very low value. Power to
the flash memory is left on in Deep sleep mode, allowing a very quick wake-up.
Power-down mode: Power-down mode does everything that Deep sleep mode does, but also
turns off the power to the IRC oscillator and flash memory. This saves more power but requires
waiting for resumption of flash operation before code execution or data access can resume.
Deep power-down mode: The Deep power-down mode can only be entered from the RTC block.
In Deep power-down mode, power is shut off to the entire chip except for the RTC module and the
RESET pin. The LPC1768 can wake up from Deep power-down mode via the RESET pin or an
alarm time match event of the RTC.
Wake-up interrupt controller: The wake-up Interrupt Controller (WIC) allows the CPU to wake up
automatically from any enabled priority interrupt that can occur while the clocks are stopped in
Deep sleep mode, Power-down mode and Deep power-down mode.
The WIC works with the Nested Vectored Interrupt Controller (NVIC). When the CPU enters
Deep sleep mode, Power-down mode or Deep power-down mode, the NVIC sends a mask of the
current interrupt situation to the WIC. This mask includes all of the interrupts that are both
enabled and of sufficient priority to be serviced immediately. With this information, the WIC
notices when one of the interrupts has occurred and then it wakes up the CPU. The WIC
eliminates the need to periodically wake up the CPU and poll the interrupts.