User's Guide

ATOP3.5G Product Description
80447ST10636A rev.10 – 2015-03-03
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Mod. 0808 2011-07 Rev.2
8.1.6 Power-saving modes
8.1.6.1 Peripheral and clock control
As shown in Figure 6, the CPU clock rate can also be controlled as needed by changing clock
sources, reconfiguring PLL values and/or altering the CPU clock divider value. This allows a trade-
off of power versus processing speed based on application requirements. In addition, Peripheral
Power Control allows shutting down the clocks to individual on-chip peripherals, allowing fine-
tuning of power consumption by eliminating all dynamic power use in any peripherals that are not
required for the application.
The LPC1768 includes three independent oscillators. These are the main oscillator, the IRC
oscillator and the RTC oscillator. Each oscillator can be used for more than one purpose as
required in a particular application. Any of the 3-clock sources can be chosen by software to
drive the main PLL and ultimately the CPU.
Following reset, the LPC1768 operates from the Internal RC oscillator until switched by software.
This allows systems to operate without any external crystal and the boot loader code to operate
at a known frequency. Main oscillator is driven by an optional external crystal on customer board.
Its presence might be required if an accurate clock is necessary, for instance for USB or HS CAN
compliancy.
Figure 6 LPC1768 clock generation
8.1.6.2 Power modes
The LPC1768 supports various power control features. There are 4 special modes of processor
power reduction:
 Sleep mode
 Deep sleep mode
 Power-down mode
 Deep power-down mode