User's Guide

ATOP3.5G Product Description
80447ST10636A rev.10 – 2015-03-03
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Reserved. Page 10 of 66
Mod. 0808 2011-07 Rev.2
7 Pinning information
7.1 Pinning
Figure 4 shows a transparent top view of ATOP 3.5G to identify all pins.
Figure 4 ATOP 3.5G pin configuration
7.2
Pin description
7.2.1 Module pinning list
Table 2 ATOP 3.5G pinning list
Symbol
[1]
Pin Level Description
[2]
Utility processor
UART0
MC_P002_TXD0_AD07 M15 3.0 transmitter output for UART0 [3]
MC_P003_RXD0_AD06 M19 3.0 receiver input for UART0 [3]
UART1
MC_P015_TXD1_SCK0_SCK V15 3.0 transmitter output for UART1 [4][5]
MC_P016_RXD1_SSEL0_SSEL T7 3.0 receiver input for UART1 [4][5]
MC_P022_RTS1_TD1 T9 3.0 ready to send [5]
MC_P017_CTS1_MISO0_MISO V13 3.0 clear to send [4][5]
MC_P021_RI1_RD1 R10 3.0 ring indicator [5]
MC_P018_DCD1_MOSI0_MOSI R11 3.0 data carrier detect [4][5]
UART2
MC_P010_TXD2_SDA2_MAT30 R13 3.0 transmitter output for UART2 [5]
MC_P011_RXD2_SCL2_MAT31 U10 3.0 receiver input for UART2 [5]