User's Guide

ATOP3.5G Product Description
80447ST10636A rev.10 – 2015-03-03
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Reserved. Page 21 of 66
Mod. 0808 2011-07 Rev.2
8.1.3 Ethernet
The Ethernet block supports bus clock rates of up to 100 MHz. It contains a full featured 10
Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance by using DMA
hardware acceleration. Features include a generous suite of control registers, half or full-duplex
operation, flow control, control frames, hardware acceleration for transmit retry, receive packet
filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-
gather DMA off-loads many operations from the CPU.
The Ethernet block and the CPU share the ARM Cortex M3 D-CODE and system bus through
the AHB-multilayer matrix to access the various on-chip SRAM blocks for Ethernet data, control
and status information.
The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII (RMII)
protocol and the on-chip Media Independent Interface Management (MIIM) serial bus.
8.1.4 USB
Device and host controller with on-chip PHY.
8.1.4.1 USB device controller
This controller enables Full-speed (12 Mbit/s) data exchange with a USB Host controller. It
consists of a register interface, serial interface engine, endpoint buffer memory and a DMA
controller. The serial interface engine decodes the USB data stream and writes data to the
appropriate endpoint buffer. The status of a completed USB transfer or error condition is
indicated via status registers. If enabled, an interrupt is also generated. When enabled, the DMA
controller transfers data between the endpoint buffer and the on-chip SRAM.
8.1.4.2 USB host controller
This controller enables full- and low-speed data exchange with USB devices attached to the bus.
It consists of a register interface, a serial interface engine and a DMA controller. The register
interface complies with the OHCI specification.
8.1.5 CAN
8.1.5.1 Description
The Controller Area Network (CAN) is a serial communications protocol which efficiently supports
distributed real-time control with a very high level of security. Its application domain ranges from
high-speed networks to low-cost multiplex wiring. The CAN block is intended to support multiple
CAN buses simultaneously, allowing the device to be used as a gateway, switch or router among
a number of CAN buses in industrial or automotive applications.
8.1.5.2 Features
 2 CAN controllers and buses
 Data rates to 1 Mbit/s on each bus
 32-bit register and RAM access
 Compatible with CAN specification 2.0B, ISO 11898-1
 Global Acceptance Filter recognizes 11- and 29-bit receive identifiers for all CAN buses
 Acceptance Filter can provide FullCAN-style automatic reception for selected Standard
Identifiers
 FullCAN messages can generate interrupts