User's Guide

ATOP3.5G Product Description
80447ST10636A rev.10 – 2015-03-03
Reproduction forbidden without written authorization from Telit Communications S.p.A. - All Rights
Reserved. Page 19 of 66
Mod. 0808 2011-07 Rev.2
 Serial interfaces available externally:
o 3 UARTs with fractional baud rate generation, one with modem control I/O, one
with IrDA support, all with FIFO. These reside on the APB-bus
o 1 SSP controller with FIFO and multi-protocol capabilities, as well as a SPI port,
sharing its interrupt. The SSP controller can be used with the GPDMA controller
and reside on the APB-bus
o 2 I
2
C-bus interfaces reside on the APB-bus. The I
2
C-bus interfaces are
expansion I
2
C-bus interfaces with standard port pins
o I
2
S-bus (Inter-IC Sound) interface for digital audio input or output, residing on the
APB bus. The I
2
S-bus interface can be used with the GPDMA
o 2 channels with Acceptance Filter/FullCAN mode residing on the APB-bus
 High-speed serial interfaces
o USB 2.0 Full-speed Device/Host/OTG controller with on-chip PHY and
associated DMA controller
o Ethernet MAC with RMII interface and dedicated DMA controller
o 2 CAN channels
 Other APB peripherals
o 12-bit A/D converter with input multiplexing among 7 external pins
o 10-bit D/A converter with DMA support
o 4 general-purpose timers with a total of 8 capture inputs and ten compare output
pins each. Each timer block has an external count input
o 1 PWM/Timer block with support for three-phase motor control
o Real-Time Clock (RTC) with separate power pin; clock source can be the RTC
oscillator or the APB clock oscillator
o Watchdog Timer: the watchdog timer can be clocked from the internal RC
oscillator, the RTC oscillator or the APB clock
 Standard ARM Test/Debug interface for compatibility with existing tools
 4 reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode and Deep
Power-down mode
 4 external interrupt inputs. In addition every PORT0/2 pin can be configured as an edge
sensing interrupt
 Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt)
 Brownout detection with separate thresholds for interrupt and forced reset
 On-chip Power-On Reset
 On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz
o For CAN and USB, a clock generated internally to ATOP 3.5G is provided or an
external crystal can be used
 On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the main oscillator, the internal RC oscillator or
the RTC oscillator
 Versatile pin function selections allow more possibilities for using on-chip peripheral
functions