User's Guide

ATOP3.5G Product Description
80447ST10636A rev.10 – 2015-03-03
Reproduction forbidden without written authorization from Telit Communications S.p.A. - All Rights
Reserved. Page 18 of 66
Mod. 0808 2011-07 Rev.2
8 Functional description
8.1 Utility Processor
The LPC1768 Utility Processor is responsible for tasks such as:
 booting the system
 handling RTC and regular wake-up
 interfacing with external sensors, display, buttons via I
2
C-bus, SPI-bus, UART, ...
 communicating with others car’s units via CAN, UART, Ethernet, ...
 controlling operator access for firmware upgrade, data retrieval via USB, UART, ...
 managing eCall access through the lower layers of the application processor. Due to
license restrictions, only service calls are allowed from the J9 VM, no eCalls.
 monitoring internal thermal sensor
Except for a few services provided by TELIT to handle communication between the
applications running on the Virtual Machine and virtualized external devices, the Utility
Processor is completely available to the application developer.
8.1.1 General features
 ARM Cortex-M3 microcontroller, running up to 100 MHz
 512 KB on-chip Flash Program Memory with In-System Programming (ISP) and In-
Application Programming (IAP) capabilities. Single Flash sector or full-chip erase in 100
ms and 256 bytes programming in 1 ms. Flash program memory is on the ARM local bus
for high performance CPU access
o 10000 erase cycles
4
o 10 years retention powered on; 20 years powered off
o First 16 erase block are 4 KB large, others are 32 KB large
 64 KB RAM memory:
o 32 KB Static RAM with local code/data bus for high-performance CPU access
o 2 * 16 KB Static RAM blocks with separate access paths for higher throughput,
for Ethernet, USB, DMA memory as well as for CPU code and data
o These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well
as for general-purpose CPU instruction and data storage for general-purpose
SRAM
 Multilayer AHB matrix interconnect with separate bus for each AHB master, providing
simultaneous DMA and program execution from on-chip flash with no contention
between these functions
 Nested Vectored Interrupt Controller (NVIC), supporting up to 33 vectored interrupts
 8 channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that
can be used with the SSP, serial interfaces, the I2S-bus port, as well as for memory-to-
memory transfers
4
If data needs to be saved regularly by utility processor, it is advised to use an external EEPROM connected to I
2
C-bus or
SPI-bus.