User's Guide

ATOP3.5G Product Description
80447ST10636A rev.10 – 2015-03-03
Reproduction forbidden without written authorization from Telit Communications S.p.A. - All Rights
Reserved. Page 16 of 66
Mod. 0808 2011-07 Rev.2
Symbol
[1]
Pin Level Description
[2]
Unused
A2; W13
[1] Pin names aree encoded as follows: MC_Pxyy_iii_jjj_kkk indicates a microcontroller pin. Each pin can
be configured between several functions (typically 4), all mentioned in the pin name:
Pxyy: GPIO yy of GPIO port x;
AD0x: ADC input x;
EINTx: external interrupt x;
MATxy: match output for timer x, channel y;
PCAPxy: capture input for PWM x, channel y;
PWMxy: PWM x, channel y;
RDx/TDx: CAN port x;
SDx/SCLx: I
2
C-bus x;
TXx/RXy: UART x;
BB_xxx indicates a pin connected respectively to baseband;
GPS_xxx indicates a pin connected respectively to GPS/GLONASS;
NFC_xxx: indicates a pin connected respectively to NFC;
Vxxx_REF indicates a voltage reference – no current should be drawn from this pin;
Vxxx_SNK indicates a voltage sink – current is drawn by this pin;
Vxxx_SRC indicates a current source – current can be drawn from this pin.
[2] Only the main function is described for microcontroller pins, but all functions available for a given pin
can be found in its name.
[3] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input.
When configured as an ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant.
[4] SSP0 is used internally and therefore is not available for customer application.
[5] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
[6] V14 and N11 optionally connected to BB_UART_RX/BB_UART_TX for debugging.
[7] Open-drain 5 V tolerant digital I/O pad, compatible with I
2
C-bus 400 kHz specification. This pad
requires an external pull up to provide output functionality. When power is switched off, this pin is
connected to the I
2
C-bus and does not disturb the I
2
C-bus lines. Open-drain configuration applies to
all functions on this pin.
[8] 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
[9] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification,
revision 2.0 (Full-speed and Low-speed mode only). This pad is not 5 V tolerant.
[10] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When
configured as the DAC output, digital section of the pad is disabled.
[11] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. Internal pull up and pull
down resistors disabled.
[12] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and internal pull up
resistor.
[13] The VBAT_SNK and VBAT_PA_SNK pins should be supplied only whenever VBAT_MC_SNK is
supplied.
[14] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
[15] Cellular antennas switchable under control of the utility processor.
[16] A minimum current of 1 mA is required to minimize insertion loss. Maximum rating pin diode 100 mA.