User's Manual

Table Of Contents
xN930 M.2 Hardware User Guide
1VV0301078 Rev.6 – 2013-11-12
3
M.2 Module Interface Details
This section provides details on the various interfaces available M.2 modules.
3.1
USB 2.0 High-Speed IPC Interface
The host processor, connected via a USB 2.0 High-speed interface, has access to the
functions of the WWAN card. The USB port is the interprocessor communications
interface with the host system.
The device classes supported are: CDC-MBIM, CDC-ACM, and CDC-NCM.
The USB Controller is compliant to the USB 2.0 Specification and with the Link Power
Management (LPM) Addendum. LPM introduces a new sleep state (L1) which significantly
reduces the transitional latencies between the defined power states; hence, improving the
responsiveness of the WWAN platform regarding connecting to the internet (Quick Connect).
USB2.0 LPM L1 Support
Support for OS assisted fast dormancy
Selective Suspend support
Very low power when in Selective Suspend: <4mw when connected
to network (wake), <1 mW no wake
It supports High-speed (HS, 480 MBit/s); Full-speed (FS, 12 MBit/s) transfers. Low- speed
mode is not supported. Because there is not a separate USB-controlled voltage bus, USB
functions implemented on the M.2 module are expected to report as self-powered devices
General Features
In device mode : High-speed (480 MBit/s) and Full-speed (12 MBit/s)
In host mode: High-speed (480 MBit/s), Full-speed (12 MBit/s). Low-speed mode
(1.5
Mbit/s) is not supported.
Support for 16 bidirectional end points and channels including the end point 0.
Table 5 USB HS Interprocessor Communications In
ter
face
Signal Name
Description
Pin
Direction
(WWAN)
Voltage
Level
USB_D+
USB Data Plus
7
I, O
2.85 V
USB_D
USB Data
Minus
9
I, O
2.85 V
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