User's Manual

LE940B6 Hardware User Guide

1VV0301331 Rev. 1.8 - 2017-03-15

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6.2.2. Thermal Design Guidelines

The thermal design for the power supply heat sink must be done with the following specifications:

• Average current consumption during LTE 2xCA DL Max throughput @PWR level max in

LE940B6: 1250 mA

NOTE:

The average consumption during transmission depends on the power level at which the device is

requested to transmit via the network. Therefore, the average current consumption varies

significantly.

In LTE mode, the LE940B6 emits RF signals continuously during transmission. Therefore, pay

special attention to how the generated heat is dissipated.

The current consumption is up to about 1250 mA in 2xCA Max throughput, and 1250 mA in LTE

continuously at the maximum Tx output power 23.0 dBm.

The current consumption is up to about 1250 mA continuously at the maximum Tx output power

(23 dBm). Therefore, make sure on the PCB used to mount LE940B6, that the area under the

LE940B6 module is as large as possible. Make sure that the LE940B6 is mounted on the large

ground area of application board and provide many ground vias to dissipate the heat.

6.2.3. Power Supply PCB Layout Guidelines

As seen in the electrical design guidelines, the power supply must have a low ESR capacitor on the

output to cut the current peaks and a protection diode on the input to protect the supply from

spikes and polarity inversion. The placement of these components is crucial for the correct

operation of the circuitry. A misplaced component can be useless or can even decrease the power

supply performances.

• The bypass low ESR capacitor must be placed close to the LE940B6 power input pads, or if the

power supply is of a switching type, it can be placed close to the inductor to cut the ripple, as

long as the PCB trace from the capacitor to LE940B6 is wide enough to ensure a drop-less

connection even during the 2A current peaks.

• The protection diode must be placed close to the input connector where the power source is

drained.

• The PCB traces from the input connector to the power regulator IC must be wide enough to

ensure that no voltage drops occur during the 2A current peaks.

Note that this is not done to save power loss but especially to avoid the voltage drops on the

power line at the current peaks frequency of 216 Hz that will reflect on all the components

connected to that supply (also introducing the noise floor at the burst base frequency.)

For this reason while a voltage drop of 300-400 mV may be acceptable from the power loss

point of view, the same voltage drop may not be acceptable from the noise point of view. If

your application does not have an audio interface but only uses the data feature of the

LE940B6, this noise is not so disturbing, and the power supply layout design can be more

forgiving.