User's Manual

LE940B6 Hardware User Guide
1VV0301331 Rev. 1.8 - 2017-03-15
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3.3. LGA Pads Layout
Figure 2: LGA Pads Layout LE940B6 334 Pads Top View
(*) MMC is not supported, and the pins assigned for it became Reserved
NOTE:
The pin defined as RFU must be considered RESERVED and not connected to any pin in the
application. The related area on the application must be kept empty.
ZZ A B C D E F G H J K L M N P R S T U V W X Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AS AT AU AV
101
GND G ND GND GND GND GND GND GND GND
101
0
GND RFU RFU RFU RFU RFU GND GND GND GND GND GND GND GND GND GND GND GN D GND RFU GND
0
1
GND RFU RFU GND
GPIO_2
1
GPIO_2
2
GND GND
ANT_GP
S
GND GND GN D GND ANT _1 GND GND GND RFU RFU
ON_OFF
_N
GND
1
2
MIC1_M
T-
RFU RFU
JTAG_R
TCK
JTAG_T
RST_N
JTAG_T
MS
GND GND GN D RFU GND G ND GND GND GND G ND GND GND G ND RFU RFU
2
3
RFU
MIC1_M
T+
GND
JTAG_R
ESOUT_
N
JTAG_T
CK
JTAG_T
DO
JTAG_T
RIGIN
GND RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU GND RFU
STAT_L
ED
3
4
EAR1_M
T-
GND
JTAG_T
DI
RFU RFU
JTAG_P
TI_CLK
JTAG_P
TI_DAT
A0
JTAG_P
TI_DAT
A1
JTAG_P
TI_DAT
A2
JTAG_P
TI_DAT
A3
RFU RFU RFU RFU RFU RFU RFU
GPIO_2
0
GND GND RFU
4
5
RFU
EAR1_M
T+
ADC_IN
1
JTAG_T
RIGOUT
RFU GND GND GND
5
6
GND GND
ADC_IN
2
MIC_BIA
S
RFU GND GND RFU
6
7
RFU SI MIN1 GND
ADC_IN
3
RFU GND GND GND
7
8
SIMVCC
1
DVI_RX RFU
ETH_RS
T_N
GND GND GN D GND
RESET_
N
GND GND GND
8
9
RFU SI MIO1 DVI_TX
GPIO_0
1
GND GND GN D
UART3_
TXD
GND GND
ANT_DI
V_1
9
10
SIMCLK
1
DVI_CL
K
GPIO_0
2
ETH_IN
T_N
GND GND GN D GND SW_RDY GND G ND GND
10
11
RFU
SIMRST
1
DVI_WA
0
GPIO_0
3
GND GND GN D
UART3_
RXD
GND GND GN D
11
12
GND RFU
GPIO_0
4
MAC_MD
IO
GND GND GN D GND SHDN_N G ND GND GND
12
13
RFU GND I2C_SDA
GPIO_0
5
UART3_
RTS
GND GND RFU
13
14
RFU I 2C_SCL
GPIO_0
6
MAC_MD
C
RFU GND GND G ND
14
15
RFU GND
SIMVCC
2
RFU
UART3_
CTS
GND GND GN D
15
16
RFU
SIMCLK
2
SIMIO2
MAC_TX
EN_ER
RFU
MAC_GT
X_CLK
MAC_TX
D[3]
MAC_TX
D[2]
MAC_TX
D[1]
MAC_TX
D[0]
MAC_RX
DV_ER
RFU
MAC_RX
_CLK
MAC_RX
D[3]
MAC_RX
D[2]
MAC_RX
D[1]
MAC_RX
D[0]
GND GND GN D GND
16
17
RFU GND
SIMRST
2
VRTC VPP
VIO_1.8
V
RFU
VAUX/P
WRMON
RFU RFU RFU RFU RFU RFU RFU RFU GND GND VBATT
VBATT_
PA
VBATT_
PA
17
18
USB_VB
US
SIMIN2 GND G ND
GPIO_1
2
GPIO_1
1
SPI_CS
GPIO_0
7
GND GND GN D
C105/RT
S
C108/DT
R
C109/DC
D
C107/DS
R
C125/RI
NG
GND GND VBATT
VBATT_
PA
GND
18
19
GND RFU USB_D+ USB_D- GND
SPI_MO
SI
SPI_ MIS
O
SPI_CL
K
GPIO_0
8
GPIO_0
9
GPIO_1
0
GND
TXD_AU
X
RXD_AU
X
C104/RX
D
C103/TX
D
C106/CT
S
GND VBATT
VBATT_
PA
VBATT_
PA
19
20
GND RFU RFU RFU RFU GND GND RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU VBATT
VBATT_
PA
GND
20
102
GND G ND GND GND GND GND GND GND GND
102
ZZ A B C D E F G H J K L M N P R S T U V W X Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP AR AS AT AU AV
LE940B6 (40 mm X 40 mm) Form Factor Pin MAP
TOP VIEW