User's Manual

LE910 Hardware User Guide
1vv0301089 Rev.3 – 09-06-2014
Reproduction forbidden without Telit Communications S.p.A. written authorization - All Rights Reserved page 56 of 79
Where not specifically stated, all the interface circuits work at 1.8V CMOS logic levels.
The following table shows the logic level specifications used in the LE910 interface circuits:
Absolute Maximum Ratings -Not Functional
Parameter
Min
Max
Input level on any digital pin (CMOS 1.8) with
respect to ground
-0.3V
2.16V
Operating Range - Interface levels (1.8V CMOS)
Level
Min
Max
Input high level
1.5V
2.1V
Input low level
0V
0.5V
Output high level
1.35V
1.8
Output low level
0V
0.45V
The GPIO pads, when used as inputs, can be connected to a digital output of another device and
report its status, provided this device has interface levels compatible with the 1.8V CMOS levels
of the GPIO. If the digital output of the device to be connected with the GPIO input pad has
interface levels different from the 1.8V CMOS, then it can be buffered with an open collector
transistor with a 10K pull up to 1.8V.
NOTE:
In order to avoid a back powering effect it is recommended to avoid having any HIGH logic
level signal applied to the digital pins of the LE910 when the module is powered off or during
an ON/OFF transition.
The GPIO pads, when used as outputs, can drive 1.8V CMOS digital devices or compatible
hardware. When set as outputs, the pads have a push-pull output and therefore the pull-up
resistor may be omitted.