User's Guide

LE910Cx HW User Guide
Doc#: 1VV0301298
Rev. 13.0 Page 69 of 124 2019-07-15
Table 25: Ethernet Control Interface Signals
PAD
Signal
I/O
Function
Type
Comment
C2
MAC_MDC
O
MAC to PHY Clock
2.85V
Logic Level
Specifications are shown
in Section 4.3.7, SIM
Card Pads @2.95V,
Table 16
C1
MAC_MDIO
I/O
MAC to PHY Data
2.85V
D1
ETH_RST_N
O
Reset to Ethernet PHY
2.85V
G4
ETH_INT_N
I
Interrupt from Ethernet
PHY
1.8V
Logic Level
Specifications are shown
in Table 11
NOTE:
The Ethernet control interface is shared with USIM2 port!
When Ethernet PHY is used, USIM2 port cannot be used (and vice versa).
NOTE:
ETH_INT_N is a 1.8V input. It has an internal pull up to 1.8V inside the
module thus it should be connected to an open drain interrupt pin of the
Ethernet PHY. In case the PHY does not support 1.8V I/O, proper level
shifter needs to be used.