User's Manual

HE910 Hardware User Guide
1vv0300925 Rev.28 – 2015-06-24
Reproduction forbidden without Telit Communications S.p.A. written authorization - All Rights Reserved page 21 of 21
3.1.3 LGA Pads Layout (HE910-EUD/EUR, HE910-NAD/NAR
and HE910-GL)
TOP VIEW
A B C D E F G H J K L M N P R
1 ADC_IN1 RES RES GND RES GND GND GND ANT GND VBATT
VBATT_
PA
VBATT_
PA
2 GND RES RES RES GND GND GND GND GND GND GND VBATT
VBATT_
PA
VBATT_
PA
GND
3
SIMVC
C
RES RES RES RES RES RES RES RES RES RES GND GND GND GND
4 SIMIN RES RES GND GND GND GND GND
5 SIMIO RES RES GND GND GND
6 SIMCLK DVI_RX RES GND GND GND
7
SIMRS
T
DVI_TX RES RES RES RES
8 RES DVI_CLK GPIO_01 RES GND GND
9 RES
DVI_WA
0
GPIO_02 RES GND RES
10 RES RES GPIO_03 RES GND GND
11
HSIC_U
SB_ST
RB
RES GPIO_04 RES RES
VAUX/P
WRMON
12
HSIC_U
SB_DA
TA
RES GPIO_06 RES GND RES RES
ON_OFF
*
13 VUSB GND GPIO_07
VDD_IO
1
1V8_SEL RES RES RES RES RES RES RES RES GND
HW_SH
UTDOW
N*
14 RES GPIO_05 VRTC RES GND RES RES RES RES RES
C105/RT
S
C108/DT
R
C109/DC
D
C107/DS
R
C125/RI
NG
15 USB_D+ USB_D- TX AUX RX AUX SPI_CLK GPIO_10
SPI_MR
DY
SPI_SR
DY
GPIO_08 GPIO_09
C104/RX
D
C103/TX
D
C106/CT
S
NOTE:
The pin defined as RES has to be considered RESERVED and not connected on any pin in the
application.