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ManualsBrandsTelit Communications ManualsElectronicsQuad-Band GSM/GPRS module -Model: GE863-PRO3
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GE863-PRO
3
Product Description
80285ST10036a Rev. 1 DRAFT- 24/04/08
Reproduction forbidden without Telit Communications S.p.A. written authorization - All Rights Reserved page 32 of 53
4.4 USARTs
The Application processor has 1 Full (9 wires) RS232 USART , 3 USART with Hardware Flow
Control, 2 two wire UARTs.
4.5 SPI bus
The Application processor has 2 set of Serial Peripheral Interfaces buses, SPI0 and SPI1. Each of
these SPI bus has four Chip Select lines, that can be encoded to provide access to 15 peripherals
[with external CS decoding].
The CS1 of the SPI0 bus is internally connected to the Serial Flash, hence SPI0 cannot use encoded
CS and therefore only 3 other devices can be connected to the SPI0 interface. SPI1 bus can use the
encoding.
The SPI busses support Master, Multiple Master or Slave mode.
The SPI bus consists of two data lines and two control lines:
• Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the
input(s) of the slave(s).
• Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the
master. There may be no more than one slave transmitting data during any particular transfer.
• Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits.
The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is
transmitted.
• Chip Select (NPCS): This control line allows slaves to be turned on and off by hardware.
All combinations of Clock Polarity (CPOL) and Clock Phase (CPHA) is supported by the bus.
4.6 Image Sensor Interface
The Image Sensor Interface (ISI) connects a CMOS-type image sensor to the processor and provides
image capture in various formats. It does data conversion, if necessary, before the storage in memory
through DMA.
The ISI supports color CMOS image sensor and grayscale image sensors with a reduced set of
functionalities.
It supports two modes of synchronization:
• Hardware with ISI_VSYNC and ISI_HSYNC signals
• International Telecommunication Union Recommendation ITU-R BT.656-4 Startof-Active-
Video (SAV) and End-of-Active-Video (EAV) synchronization sequence.
Using EAV/SAV for synchronization reduces the pin count (ISI_VSYNC, ISI_HSYNC are not used).
The polarity of the synchronization pulse is programmable to comply with the sensor signals.