User manual

Table Of Contents
Part 6: IEEE 488.2 Command Reference
Short Long What The Command or Query Does
DERR
DD_ERR_NUM Displays the section of waveform containing the specified DDA error
number.
DFBIT?
DD_FIND_BITCELL? Looks at the head signal and attempts to determine the bit-cell time.
DFEN
DD_FIR_ENABLE Enables the FIR filter for PRML channel emulation.
DFER
DD_FIND_ERROR Commands the DDA to find errors.
DFGD
DD_CTAF_GROUP_DELAY Sets the DDA CTAF parameter, group delay.
DFIR
DD_FIR Stores the setup that will be used if the FIR filter is enabled for use in
the channel emulation.
DHSC
DD_HEADSIGNAL_CHANNEL
Specifies the head signal source channel or memory for channel
emulation and servo analysis.
DIGS
DD_IGNORE_SAMPLES
Defines number of samples to be ignored at the Read Gate signal end
for channel emulation and analog compare.
DNER?
DD_NUM_ERRORS Gives the number of DDA errors found.
DOVL
DD_OVERLAP_REF Sets a state variable that determines whether the DDA
re-establishes the overlap of the reference signal whenever the head
trace is moved.
DPA
DD_PES_ANALYSIS Starts/aborts PES analysis.
DPD?
DD_PES_DATA? Reads out results of PES Analysis.
DPSD?
DD_PES_SUMMARY_DATA? Summarizes PES Analysis results.
DPSU
DD_PES_SETUP Sets parameters for PES Analysis.
DRAV
DD_RESET_AVERAGE Resets the averaged data and all sweeps; clears histograms and para-
meters.
DRCC
DD_READCLOCK_CHANNEL Specifies the input channel to which Read Clock is connected or the
memory in which it is stored.
DRGC
DD_READGATE_CHANNEL
Specifies the input channel to which Read Gate is connected or the
memory in which it is stored.
DRGP
DD_READ_GATE_POLARITY Selects the polarity of the read gate signal.
DRLE
DD_ML_RUN_LENGTH_LIMIT Limits the run length.
DRLM
DD_ML_MIN_SPACING
Sets the minimum allowed transitions.
DSAV
DD_START_AVERAGING
Changes the state of the “Avg. Samples” switch on the Graph menu.
DSEG
DD_BYTE_OFFSET_SEGMENT
Moves the head trace to show the specified segment in DDA.
DSF
DD_SHOW_FILTERED Enables and disables the filtering of the head signal.
DSIG
DD_SIGNAL_TYPE Specifies Peak Detect or a particular PRML format for the head
signal.
DSLV
DD_SHOW_LEVELS Displays the level markers indicating the Viterbi levels of the ML
samples when channel emulation is active.
DSML
DD_SHOW_ML Displays ML markers.
DSPH
DD_SAMPLE_PHASE Adjusts the phase between the DDFA PLL sample points and an
external clock reference (when RCLK is connected).
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