User Manual
Table Of Contents
- Introduction TO QPHY-DDR3
- Signals measured
- DDR3 MEASUREMENT PREPARation
- Basic Functionality
- Using Qualiphy DDR3
- QualiPHY Compliance Test Platform
- QPHY-DDR3 Test Configurations
- 1) Clock tests DDR3-1333 (1 Probe)
- 2) CKdiff-DQse-DQSdiff 1333 Write Burst (3 Probes)
- 3) CKdiff-DQse-DQSdiff 1333 Read Burst (3 Probes)
- 4) Eye Diagram (3 Probes Debug)
- 5) Eye Diagram with CS Enabled (4 Probes Debug)
- 6) CKDiff-DQse-DQS-ADD/CTRLse (4 Probes Debug)
- 7) CKdiff-DQse-DQSp-DQsn (4 probes test, each DQS signal probed single ended)
- 8) CKp-CKn-DQse-DQSdiff (4 probe test, each CK signal is probed single ended)
- 9) Vref tests
- D1) Demo of All Tests
- QPHY-DDR3 Variables
- QPHY-DDR3 Limit Sets
- QPHY-DDR3 Tests
- Clock Tests
- tCK(avg), Average Clock Period
- tCK(abs), Absolute Clock Period
- tCH(avg), Average High Pulse Width
- tCL(avg), Average Low Pulse Width
- tCH(abs), Absolute High Pulse Width
- tCL(abs), Absolute Low Pulse Width
- tJIT(duty), Half Period Jitter
- tJIT(per), Clock Period Jitter
- tJIT(cc), Cycle to Cycle Period Jitter
- tERR(n per), Cumulative Error
- Eye Diagram
- Electrical Tests
- Timing Tests
- Four Probe tests measurements using ADDR/CTL
- Clock Tests
4 917717 Rev C
Chip Select Signal Name .................................................................................................................................. 30
Script Settin gs .......................................................................................................................................................... 30
Save Acquired Waveforms ............................................................................................................................... 30
Silent mode control ........................................................................................................................................... 30
Stop On Test to review results .......................................................................................................................... 30
Use Chip Select (require one more probe) ....................................................................................................... 30
Waveform Path ................................................................................................................................................. 30
Latenc y Settin g ........................................................................................................................................................ 30
Overall Read Latency ....................................................................................................................................... 30
Overall Write Latency ....................................................................................................................................... 31
Demo Settings .......................................................................................................................................................... 31
Use Stored Waveforms ..................................................................................................................................... 31
Recalled Waveform File Index (5 digits) ........................................................................................................... 31
Define format used to set trace names ............................................................................................................. 31
Use Stored Trace for Speed Grade .................................................................................................................. 31
Advanced Settings ................................................................................................................................................... 32
Clock Period per Screen Division ..................................................................................................................... 32
Number of cycles for Clock test ........................................................................................................................ 32
Max. Number Of Samples Per Clock Period .................................................................................................... 32
Configuration Specific Variables............................................................................................................................... 32
XX Channel Gain .............................................................................................................................................. 32
XX Channel Index ............................................................................................................................................. 32
XX Channel Invert ............................................................................................................................................. 32
XX Channel Offset ............................................................................................................................................ 32
Speed Bin Paramters ............................................................................................................................................... 32
CAS Latency ..................................................................................................................................................... 32
CAS Write Latency............................................................................................................................................ 33
Speed Bin ......................................................................................................................................................... 33
QPHY-DDR3 LIMIT S ETS ....................................................................................................... 34
DDR3-800 ................................................................................................................................................................ 34
DDR3-1066 .............................................................................................................................................................. 34
DDR3-1333 .............................................................................................................................................................. 34
DDR3-1600 .............................................................................................................................................................. 34
QPHY-DDR3 TESTS ................................................................................................................ 34
Clock Test s ............................................................................................................................................................... 34
tCK(avg), Average Clock Period ................................................................................................................................ 34
tCK(abs), Absolute Clock Period ................................................................................................................................ 34
tCH(avg), Average High Pulse Width ......................................................................................................................... 34
tCL(avg), Average Low Pulse Width .......................................................................................................................... 35
tCH(abs), Absolute High Pulse Width ........................................................................................................................ 35
tCL(abs), Absolute Low Pulse Width .......................................................................................................................... 35
tJIT(duty), Half Period Jitter ....................................................................................................................................... 35
tJIT(per), Clock Period Jitter ...................................................................................................................................... 35
tJIT(cc), Cycle to Cycle Period Jitter .......................................................................................................................... 35
tERR(n per), Cumulative Error ................................................................................................................................... 36
Eye Diagram ............................................................................................................................................................ 36
Write Burst (Inputs) .................................................................................................................................................... 36
Read Burst (Outputs) ................................................................................................................................................. 36
Electrical Tests ......................................................................................................................................................... 36
Write Bursts (Inputs) ......................................................................................................................................... 36
Slew (Input Slewrate) ..................................................................................................................................................... 36
SlewR and SlewF ....................................................................................................................................................... 36
Logic Levels ................................................................................................................................................................... 37
VIH(ac), maximum AC input logic high ....................................................................................................................... 37