User Manual
Table Of Contents
- Introduction TO QPHY-DDR3
- Signals measured
- DDR3 MEASUREMENT PREPARation
- Basic Functionality
- Using Qualiphy DDR3
- QualiPHY Compliance Test Platform
- QPHY-DDR3 Test Configurations
- 1) Clock tests DDR3-1333 (1 Probe)
- 2) CKdiff-DQse-DQSdiff 1333 Write Burst (3 Probes)
- 3) CKdiff-DQse-DQSdiff 1333 Read Burst (3 Probes)
- 4) Eye Diagram (3 Probes Debug)
- 5) Eye Diagram with CS Enabled (4 Probes Debug)
- 6) CKDiff-DQse-DQS-ADD/CTRLse (4 Probes Debug)
- 7) CKdiff-DQse-DQSp-DQsn (4 probes test, each DQS signal probed single ended)
- 8) CKp-CKn-DQse-DQSdiff (4 probe test, each CK signal is probed single ended)
- 9) Vref tests
- D1) Demo of All Tests
- QPHY-DDR3 Variables
- QPHY-DDR3 Limit Sets
- QPHY-DDR3 Tests
- Clock Tests
- tCK(avg), Average Clock Period
- tCK(abs), Absolute Clock Period
- tCH(avg), Average High Pulse Width
- tCL(avg), Average Low Pulse Width
- tCH(abs), Absolute High Pulse Width
- tCL(abs), Absolute Low Pulse Width
- tJIT(duty), Half Period Jitter
- tJIT(per), Clock Period Jitter
- tJIT(cc), Cycle to Cycle Period Jitter
- tERR(n per), Cumulative Error
- Eye Diagram
- Electrical Tests
- Timing Tests
- Four Probe tests measurements using ADDR/CTL
- Clock Tests
34 917717 Rev C
QPHY-DDR3 LIMIT SETS
DDR3-800
This corresponds to the JEDEC JESD79-3D DDR3 standard specification limits for 800 MT/s.
DDR3-1066
This corresponds to the JEDEC JESD79-3D DDR3 standard specification limits for 1066 MT/s.
DDR3-1333
This corresponds to the JEDEC JESD79-3D DDR3 standard specification limits for 1333 MT/s..
DDR3-1600
This corresponds to the JEDEC JESD79-3D DDR3 standard specification limits for 1600 MT/s.
QPHY-DDR3 TESTS
Clock Tests
All time measure on clock CK are done at level VREF.
tCK(avg), Average Clock Period
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each
clock period is calculated from rising edge to rising edge.
tCK(abs), Absolute Clock Period
tCK(abs) is defined as the absolute clock period, as measured from one rising edge to the next
consecutive
rising edge. tCK(abs) is not subject to production test.
tCH(avg), Average High Pulse Width
tCH(avg) is defined as the average high pulse width, as calculated across any cons ec uti ve 200 high
pulses.