User Manual
Table Of Contents
- Introduction TO QPHY-DDR3
- Signals measured
- DDR3 MEASUREMENT PREPARation
- Basic Functionality
- Using Qualiphy DDR3
- QualiPHY Compliance Test Platform
- QPHY-DDR3 Test Configurations
- 1) Clock tests DDR3-1333 (1 Probe)
- 2) CKdiff-DQse-DQSdiff 1333 Write Burst (3 Probes)
- 3) CKdiff-DQse-DQSdiff 1333 Read Burst (3 Probes)
- 4) Eye Diagram (3 Probes Debug)
- 5) Eye Diagram with CS Enabled (4 Probes Debug)
- 6) CKDiff-DQse-DQS-ADD/CTRLse (4 Probes Debug)
- 7) CKdiff-DQse-DQSp-DQsn (4 probes test, each DQS signal probed single ended)
- 8) CKp-CKn-DQse-DQSdiff (4 probe test, each CK signal is probed single ended)
- 9) Vref tests
- D1) Demo of All Tests
- QPHY-DDR3 Variables
- QPHY-DDR3 Limit Sets
- QPHY-DDR3 Tests
- Clock Tests
- tCK(avg), Average Clock Period
- tCK(abs), Absolute Clock Period
- tCH(avg), Average High Pulse Width
- tCL(avg), Average Low Pulse Width
- tCH(abs), Absolute High Pulse Width
- tCL(abs), Absolute Low Pulse Width
- tJIT(duty), Half Period Jitter
- tJIT(per), Clock Period Jitter
- tJIT(cc), Cycle to Cycle Period Jitter
- tERR(n per), Cumulative Error
- Eye Diagram
- Electrical Tests
- Timing Tests
- Four Probe tests measurements using ADDR/CTL
- Clock Tests
32 917717 Rev C
Ad vanced Set t ings
Clock Period per Screen Division
Oscilloscope timebase and sampling rate is set to acquire the given number of clock cycle per display
horizontal division at a given DUT Speed Grad in MT/s and for a Max. Number of Samples Per Clock
Period. The default is 3341 clock periods (this gives a 10us/div timebase at 667 MT/s and 3.3MS max for
100 samples per period).
Timebase = [Clock Period Per Screen Division] / ([DUT Speed Grade in MT/s] / 2 * 1e6)
Maximum Samples = [Max. Num ber Of Samp le s Per Clock Per io d] * [Cl o c k Pe rio d Per Scr ee n
Division] * 10
Number o f cy cl es for C lock test
Jedec standard requires 200 cycles for the Clock compliance test.
This is the default value of this variable. Any positive number can be entered.
Max. Number Of Samples Per Clock Period
The oscilloscope timebase and sampling rate is set to acquire the given number of points per clock
period. The oscilloscope is always set to at least acquire at 20GS/s. Also, if an oscilloscope with greater
than 6GHz bandwidth is used, the bandwidth is limited to 6GHz. See the Clock Period Per Screen
Division topic for more details. Choose between 10;20;50;100;200;500 or 1000. The default value is 100.
Configuration Specific Variables
The following variables are specific to the configuration in which they appear under. Some of these
variables appear under multiple configurations.
XX Channel Gain
Allows the user to manually specify the vertical scale in V/div for XX SUT. XX can be Clock, DQ, DQS,
DQSn, ADD/CTRL, or DM. The default is 0 for auto-scale.
XX Channel Index
Allows the user to manually specify the channel XX SUT. XX can be Clock, DQ, DQS, DQSn, A DD/CTRL,
or DM. Default is 1 for CK, 2 for DQS, 3 for DQ and 4 for others
XX Channel Invert
Allows the user to invert XX SUT. XX can be Clock, DQ, DQS, DQSn, ADD/CTRL, or DM. The default is
False.
XX Channel Offset
Allows the user to manually specify the offset in Volts for XX SUT. XX can be Clock, DQ, DQS, DQSn,
ADD/CTRL, or DM. The default is 0 for auto-scale.
Speed Bin Paramters
CAS Latency
Allows the user to specify the CAS Latency (CL) used to define tCK(avg) limits (see tables 61 to 64 in
JEDEC Standard).