User Manual
Table Of Contents
- Introduction TO QPHY-DDR3
- Signals measured
- DDR3 MEASUREMENT PREPARation
- Basic Functionality
- Using Qualiphy DDR3
- QualiPHY Compliance Test Platform
- QPHY-DDR3 Test Configurations
- 1) Clock tests DDR3-1333 (1 Probe)
- 2) CKdiff-DQse-DQSdiff 1333 Write Burst (3 Probes)
- 3) CKdiff-DQse-DQSdiff 1333 Read Burst (3 Probes)
- 4) Eye Diagram (3 Probes Debug)
- 5) Eye Diagram with CS Enabled (4 Probes Debug)
- 6) CKDiff-DQse-DQS-ADD/CTRLse (4 Probes Debug)
- 7) CKdiff-DQse-DQSp-DQsn (4 probes test, each DQS signal probed single ended)
- 8) CKp-CKn-DQse-DQSdiff (4 probe test, each CK signal is probed single ended)
- 9) Vref tests
- D1) Demo of All Tests
- QPHY-DDR3 Variables
- QPHY-DDR3 Limit Sets
- QPHY-DDR3 Tests
- Clock Tests
- tCK(avg), Average Clock Period
- tCK(abs), Absolute Clock Period
- tCH(avg), Average High Pulse Width
- tCL(avg), Average Low Pulse Width
- tCH(abs), Absolute High Pulse Width
- tCL(abs), Absolute Low Pulse Width
- tJIT(duty), Half Period Jitter
- tJIT(per), Clock Period Jitter
- tJIT(cc), Cycle to Cycle Period Jitter
- tERR(n per), Cumulative Error
- Eye Diagram
- Electrical Tests
- Timing Tests
- Four Probe tests measurements using ADDR/CTL
- Clock Tests
QPHY-DDR3 Software Opti on
917717 Rev C 3
TABLE OF CONT E NTS
INTRODUCTION TO QPHY-DDR3 ............................................................................................ 7
Required equ ipment ................................................................................................................................................... 7
SIGNALS MEASURED .............................................................................................................. 7
CK, CK# Input ............................................................................................................................................................ 7
DQ Input/Output ......................................................................................................................................................... 7
DQS, DQS# Input/Output ........................................................................................................................................... 7
CS# Input ................................................................................................................................................................... 7
BASIC FUNCTIONALITY .......................................................................................................... 8
READ Burst Operation ............................................................................................................................................. 14
WRITE Burst Operation ........................................................................................................................................... 15
USING QUALIPHY DDR3 ........................................................................................................ 16
QUALIPHY COMPLIANCE TEST PLATFORM ....................................................................... 16
Oscilloscope Option Key Installation ........................................................................................................................ 19
Typical (Recommended) Configuration .................................................................................................................... 19
Remote (Network) Configuration ............................................................................................................................. 19
Oscilloscope Selection ............................................................................................................................................. 19
Accessing the QPHY-DDR3 Software using QualiPHY ........................................................................................... 20
Customizing QualiPHY ............................................................................................................................................. 23
QPHY-DDR3 Operation............................................................................................................................................ 25
DDR3 MEASUREMENT PREPARATION ................................................................................. 8
Deskewing the Probes ............................................................................................................................................... 8
Differential Probe Deskew Procedure using TF-DSQ on non-Zi oscilloscopes ......................................................... 8
Differential Probe Deskew Procedure on Zi oscilloscopes using PCF200 ................................................................ 8
PCF200 Fixture Overview ................................................................................................................................... 8
Probe Connection to PCF200 ............................................................................................................................. 9
Probe Calibration Menu .................................................................................................................................... 10
Probe Calibration Procedure ............................................................................................................................ 11
QPHY-DDR3 TEST CONFIGURATIONS ................................................................................ 26
1) Clock tests DDR3-1333 (1 Probe) ....................................................................................................................... 26
2) CKdiff-DQse-DQSdiff 1333 Write Burst (3 Probes) ............................................................................................. 26
3) CKdiff-DQse-DQSdiff 1333 Read Burst (3 Probes) ............................................................................................. 28
4) Eye Diagram (3 Probes Debug) ........................................................................................................................... 28
5) Eye Diagram with CS Enabled (4 Probes Debug) ............................................................................................... 28
6) CKDiff-DQse-DQS-ADD/CTRLse (4 Probes Debug) .......................................................................................... 28
7) CKdiff-DQse-DQSp-DQsn (4 probes test, each DQS signal probed single ended) ............................................ 29
8) CKp-CKn-DQse-DQSdiff (4 probe test, each CK signal is probed single ended) ............................................... 29
9) Vref tests .............................................................................................................................................................. 29
D1) Demo of All Tests ............................................................................................................................................... 29
QPHY-DDR3 VARIABLES ...................................................................................................... 29
General Variables ..................................................................................................................................................... 29
DUT Speed Grade in MT/s ............................................................................................................................... 29
DQ Signal Name ............................................................................................................................................... 30
DQS Signal Name............................................................................................................................................. 30
Clock Signal Name ........................................................................................................................................... 30
DUT Power Supply VDDQ ................................................................................................................................ 30
4
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Probe Names ...................................................................................................................................................... 30