User Manual
Table Of Contents
- Introduction TO QPHY-DDR3
- Signals measured
- DDR3 MEASUREMENT PREPARation
- Basic Functionality
- Using Qualiphy DDR3
- QualiPHY Compliance Test Platform
- QPHY-DDR3 Test Configurations
- 1) Clock tests DDR3-1333 (1 Probe)
- 2) CKdiff-DQse-DQSdiff 1333 Write Burst (3 Probes)
- 3) CKdiff-DQse-DQSdiff 1333 Read Burst (3 Probes)
- 4) Eye Diagram (3 Probes Debug)
- 5) Eye Diagram with CS Enabled (4 Probes Debug)
- 6) CKDiff-DQse-DQS-ADD/CTRLse (4 Probes Debug)
- 7) CKdiff-DQse-DQSp-DQsn (4 probes test, each DQS signal probed single ended)
- 8) CKp-CKn-DQse-DQSdiff (4 probe test, each CK signal is probed single ended)
- 9) Vref tests
- D1) Demo of All Tests
- QPHY-DDR3 Variables
- QPHY-DDR3 Limit Sets
- QPHY-DDR3 Tests
- Clock Tests
- tCK(avg), Average Clock Period
- tCK(abs), Absolute Clock Period
- tCH(avg), Average High Pulse Width
- tCL(avg), Average Low Pulse Width
- tCH(abs), Absolute High Pulse Width
- tCL(abs), Absolute Low Pulse Width
- tJIT(duty), Half Period Jitter
- tJIT(per), Clock Period Jitter
- tJIT(cc), Cycle to Cycle Period Jitter
- tERR(n per), Cumulative Error
- Eye Diagram
- Electrical Tests
- Timing Tests
- Four Probe tests measurements using ADDR/CTL
- Clock Tests
QPHY-DDR3 Software Opti on
917717 Rev C 29
• tIH (base + derated)
• tIPW
7) CKdif f-DQse-DQSp-DQsn (4 probes test, each DQS signal pr obed single ended)
• VSEH(ac)
• VSEL(ac)
• VIX(ac)
• AC Overshoot Peak Amplitude
• AC Overshoot Area above VDDQ
• AC Undershoot Peak Amplitude
• AC Undershoot Area below VSSQ
• SlewR
• SlewF
8) CKp-CKn-DQse-DQSdif f (4 probe test, each CK signal i s probed single ended)
• VSEH(ac)
• VSEL(ac)
• AC Overshoot Peak Amplitude
• AC Overshoot Area above VDDQ
• AC Undershoot Peak Amplitude
• AC Undershoot Area below VSSQ
• SlewR
• SlewF
9) Vref tes ts
• Vref(dc)
D1) Demo of All Tests
This configuration uses the saved waveforms found in the D:\Waveforms\DDR3 folder and run all of the
tests. All of the variabl es are set to their defaults except Use Stored Waveforms is set to Yes and Use
Stored Trace for Speed Grade is set to Yes. The limit set in use is DDR3-1333. All supported tests are
run.
QPHY-DDR3 VARIA BLES
General Variables
The following variables are used by all configurations. They can be used in conjunction with the test
selection and limit set selection to create custom configurations.
DU T S p e ed Gr a de in M T/ s
Transfer speed of the DUT. Used to set the oscilloscope timebase and sampling rate, see Clock Period
Per Screen Division variable for more explanation. Choose between: 800, 1066, 1333, 1600 MT/s or
custom. Default is 1333MT/s.