User Manual
Table Of Contents
- Introduction TO QPHY-DDR3
- Signals measured
- DDR3 MEASUREMENT PREPARation
- Basic Functionality
- Using Qualiphy DDR3
- QualiPHY Compliance Test Platform
- QPHY-DDR3 Test Configurations
- 1) Clock tests DDR3-1333 (1 Probe)
- 2) CKdiff-DQse-DQSdiff 1333 Write Burst (3 Probes)
- 3) CKdiff-DQse-DQSdiff 1333 Read Burst (3 Probes)
- 4) Eye Diagram (3 Probes Debug)
- 5) Eye Diagram with CS Enabled (4 Probes Debug)
- 6) CKDiff-DQse-DQS-ADD/CTRLse (4 Probes Debug)
- 7) CKdiff-DQse-DQSp-DQsn (4 probes test, each DQS signal probed single ended)
- 8) CKp-CKn-DQse-DQSdiff (4 probe test, each CK signal is probed single ended)
- 9) Vref tests
- D1) Demo of All Tests
- QPHY-DDR3 Variables
- QPHY-DDR3 Limit Sets
- QPHY-DDR3 Tests
- Clock Tests
- tCK(avg), Average Clock Period
- tCK(abs), Absolute Clock Period
- tCH(avg), Average High Pulse Width
- tCL(avg), Average Low Pulse Width
- tCH(abs), Absolute High Pulse Width
- tCL(abs), Absolute Low Pulse Width
- tJIT(duty), Half Period Jitter
- tJIT(per), Clock Period Jitter
- tJIT(cc), Cycle to Cycle Period Jitter
- tERR(n per), Cumulative Error
- Eye Diagram
- Electrical Tests
- Timing Tests
- Four Probe tests measurements using ADDR/CTL
- Clock Tests
QPHY-DDR3 Software Opti on
917717 Rev C 13
BASIC FUNCTIONALITY
The functionality is extracted from JEDEC Standard No. JESD79-3D, section 3.
The DDR3 SDRAM is a high-speed dynamic random-access mem or y internally configured as an eight -
bank DRAM. The DDR3 SDRAM uses an 8n prefetch architecture to achieve high-speed operation. The
8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write operation for the DDR3 SDRAM consists of a single 8n-bit wide, four
clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data
transfers at the I/O pins.
Read and write operation to the DDR3 SDRAM are burst oriented, start at a selected location, and
continue for a burst length of eight or a “chopped” burst of four in a programmed sequence. Operation
begins with the registration of an Active command, which is then followed by a Read or Write command.
The address bits registered coincident with the Active command are used to select the bank and row to
be activated
(BA0-BA2 select the bank; A0-A15 select the row; refer to “DDR3 SDRAM Addressing” on page 15 for
specific requirements). The address bits registered coincident with the Read or Write command are used
to select the starting column location for the burst operation, determine if the auto precharge command is
to be issued (via A10), and select BC4 or BL8 mode on the fly (via A12) if enabled in the mode register.
Prior to normal operation, the DDR3 SDRAM must be powered up and initialized in a predefined manner.