QPHY-DDR2 DDR2 Serial Data Operator’s Manual Revision A – July, 2009 Relating to the Following Release Versions: Software Option Rev. 5.9 DDR2 Script Rev. 1.0 Style Sheet Rev. 1.
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QPHY-DDR2 Software Option Table of Contents INTRODUCTION TO QPHY-DDR2 ............................................................................................ 7 Required equipment ................................................................................................................................................... 7 SIGNALS MEASURED .............................................................................................................. 7 CK, CK# Input ................................
D1) Demo of All Clock tests ..................................................................................................................................... 29 D2) Demo of Eye Diagram (Debug) ......................................................................................................................... 30 D3) Demo of All tests ...............................................................................................................................................
QPHY-DDR2 Software Option tCL(abs), Absolute Low Pulse Width .......................................................................................................................... 35 tJIT(duty), Half Period Jitter ....................................................................................................................................... 35 tJIT(per), Clock Period Jitter ............................................................................................................................
TABLE OF FIGURES Figure 1. Data output (read) timing [JESD79-2E figure 32] .................................................................................. 8 Figure 2. Burst read followed by burst write [JESD79-2E figure 35] .................................................................. 8 Figure 3. Data input (write) timing [JESD79-2E figure 38] ................................................................................... 9 Figure 4. Burst write operation [JESD79-2E figure 39] ..................
QPHY-DDR2 Software Option INTRODUCTION TO QPHY-DDR2 QPHY-DDR2 is an automated test package performing all of the real time oscilloscope tests for Double Data Rate in accordance with JEDEC Standard No. 79-2E. The software can be run on the LeCroy SDA/DDA/WavePro 740Zi and 760Zi and all SDA/DDA/WaveMaster 8Zi oscilloscopes.
Burst Read The Burst Read command is initiated by having CS# and CAS# LOW while holding RAS# and WE# HIGH at the rising edge of the clock. The address inputs determine the starting column address for the burst. The data strobe output (DQS) is driven LOW one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS).
QPHY-DDR2 Software Option Burst Write The Burst Write command is initiated by having CS#, CAS# and WE# LOW while holding RAS# HIGH at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to (AL + CL -1); and is the number of clocks of delay that are required from the time the write command is registered to the clock edge associated to the first DQS strobe.
Figure 5. Burst write followed by burst read [JESD79-2E figure 41] USING QUALIPHY DDR2 QualiPHY DDR2 guides the user, step-by-step, through each of the source tests described in JEDEC Standard No. 79-2E. To do this, the user must setup a test session. Users choose test configurations to run.
QPHY-DDR2 Software Option QUALIPHY COMPLIANCE TEST PLATFORM QualiPHY is LeCroy’s compliance test framework which leads the user through the compliance tests. QualiPHY displays connection diagrams to ensure tests run properly, automates the oscilloscope setup, and generates complete, detailed reports. The QualiPHY software application automates the test and report generation. Figure 6.
See the QualiPHY Operator’s Manual for more information on how to use the QualiPHY framework. Figure 7.
QPHY-DDR2 Software Option Oscilloscope Option Key Installation An option key must be purchased to enable the QPHY-DDR2 option. Call LeCroy Customer Support to place an order and receive the code. Enter the key and enable the purchased option as follows: 1. From the oscilloscope menu select Utilities Utilities Setup 2. Select the Options tab and click the Add Key button. 3. Enter the Key Code using the on-screen keyboard. 4. Restart the oscilloscope to activate the option after installation.
QualiPHY tests the oscilloscope connection after clicking the Start button. The system prompts you if there is a connection problem. QualiPHY’s Scope Selector function can also be used to verify the connection. Please refer to the QualiPHY Operator’s Manual for explanations on how to use Scope Selector and other QualiPHY functions. Accessing the QPHY-DDR2 Software using QualiPHY This topic provides a basic overview of QualiPHY’s capabilities.
QPHY-DDR2 Software Option 4. Click the Configuration button in the QualiPHY main menu: 5. Select a configuration from the pop-up menu: Figure 9. QualiPHY configuration selection menu 6. Click Start. 7. Follow the pop-up window prompts.
Customizing QualiPHY The predefined configurations in the Configuration screen cannot be modified. However, you can create your own test configurations by copying one of the standard test configurations and making modifications. A description of the test is also shown in the description field when selected. Figure 10.
QPHY-DDR2 Software Option Once a custom configuration is defined, script variables and the test limits can be changed by using the Variable Setup and Limits Manager from the Edit/View Configuration window. Figure 11.
QPHY-DDR2 Operation After pressing Start in the QualiPHY menu, the software instructs how to set up the test using pop-up connection diagrams and dialog boxes. Figure 12. Start button Figure 13.
QPHY-DDR2 Software Option DDR2 MEASUREMENT PREPARATION Before starting any test or data acquisition, the oscilloscope must be warmed for at least 20 minutes. Calibration is automatic under software control and no manual calibration is required. The procedure should be run again if the temperature of the oscilloscope changes by more than a few degrees. Differential Probe Deskew Procedure using TF-DSQ Note: Another procedure can be used for Zi oscilloscopes, refer to the next section for details.
PCF200 Fixture Overview Probe Connection to PCF200 Probe Calibration Menu D620 Probe Calibration Advanced mode is available: Advanced Mode Probe Calibration Menu Advanced Probe Calibration Read about PCF200 fixture Connecting probes to the circuit under test can be a difficult procedure.
QPHY-DDR2 Software Option PCF200 Fixture Overview Major components of the PCF200 fixture are shown in the following figure: SMA male connector Fast Edge input. SMA female connector output to AUX IN for 50-ohm termination. Clip for connection of Solder-In probes. 2-pins header for connection of Square-Pin probes. Figure 14. PCF200 Deskew Fixture A SMA male to BNC male 50-ohm cable is required to perform the calibration. System assembly is accomplished in the following steps: 1.
Probes are connected electrically in a single-ended arrangement: the positive (+) side of the probe must be connected to the signal trace, while the negative (-) side is connected to the ground plane. Figure 15. Differential probe properly connected to the fixture (Solder-In configuration) Probe Calibration Menu The probe calibration menu can be accessed from the Vertical drop-down menu or from the channel dialog: Figure 16.
QPHY-DDR2 Software Option Figure 17. Basic Probes Calibration menu The information in the probe calibration menu is organized such that each row represents the information for a given channel, and each column represents the calibration information or control for that channel. For each channel, the information and control provided includes: The channel number in the colored button icon and the probe type that is installed. A Full Calibration button, which starts the calibration. Use only with TF-DSQ.
Skew This field shows the measured skew between the probe in the specified channel and the reference channel. This can be entered manually or as the result of an automatic calibration. In the case of automatic calibration, it can be the result of a portion of the full calibration or it can be the result of a standalone deskew calibration. Even after the deskew has been performed automatically, the deskew correction can be adjusted manually.
QPHY-DDR2 Software Option Checking this box allows: Calibration of gain/offset only Calibration of deskew only Access to the advanced menu (shown as a tab behind the "Probes Cal" dialog) Gain/Offset Only Pressing this button performs only the DC calibration of the probe on the specified channel. See details of DC Calibration Theory of Operation in TF-DSQ Operation Manual. DO NOT use with PCF200 connected to Fast Edge output.
Differential (or Single-Ended) Probe Selection The PCF200 fixture calibrates probes differentially or in single-ended mode depending on the type of probe used. The selection is done automatically when the probe is detected. If No Probe is detected, the selection is done manually. When calibrating D620 probes, they are automatically detected and Differential is checked. Deskew All (or Common Skew) This is the deskew amount applied to all channels.
QPHY-DDR2 Software Option QPHY-DDR2 TEST CONFIGURATIONS Configurations include variable settings and limit sets as well, not just test selections. See the section for a description of each variable value and its default value. See the QPHY-DDR2 Limit Sets section for more information about the limit sets. 1) Clock tests DDR2-667 (1 Probe) This configuration runs all of the clock tests. All of the variables are set to their defaults. The limit set in use is DDR2-667.
tDS(base) tDH(base) tWPRE tWPST 3) CKdiff-DQse-DQSdiff 667 Read Burst (3 probes) This configuration runs all of the tests that are run on read bursts of the DDR2 signals in which 3 probes are required. All of the variables are set to their defaults. The limit set in use is DDR2-667.
QPHY-DDR2 Software Option tDS1(base) tDH1(base) SlewR (on Add/Ctrl signal) SlewF (on Add/Ctrl signal) VIH(ac) (on Add/Ctrl signal) VIH(dc) (on Add/Ctrl signal) VIL(ac) (on Add/Ctrl signal) VIL(dc) (on Add/Ctrl signal) VSWING (on Add/Ctrl signal) AC Overshoot Peak Amplitude (on Add/Ctrl signal) AC Overshoot Area above VDDQ (on Add/Ctrl signal) AC Undershoot Peak Amplitude (on Add/Ctrl signal) AC Undershoot Area below VSSQ (on Add/Ctrl signal) tIS(base) (
D2) Demo of Eye Diagram (Debug) This configuration uses the saved waveforms found in the D:\Waveforms\DDR2 folder and run the Eye Diagram test on the read bursts and the write bursts. All of the variables are set to their defaults except Use Stored Waveforms is set to Yes and Use Stored Trace for Speed Grade is set to Yes. The limit set in use is DDR2-667.
QPHY-DDR2 Software Option QPHY-DDR2 VARIABLES General Variables The following variables are used by all configurations. They can be used in conjunction with the test selection and limit set selection to create custom configurations. DUT Speed Grade in MT/s Transfer speed of the DUT. Used to set the oscilloscope timebase and sampling rate, see Clock Period Per Screen Division variable for more explanation. Choose between: 400, 533, 667 and 800 MT/s. Default is 667 MT/s.
Silent mode control No more interaction with the user when silent mode is on. Choose between Yes or No. Default is No. This is useful to let the test run without interruption in the background. Stop On Test to review results When set to Yes, the script stops after each test allowing you to view the results. The setup is saved so the oscilloscope settings can be modified by the user. On resume, the setup is recalled. Any new acquisition done may cause the script to produce unexpected results.
QPHY-DDR2 Software Option Configuration Specific Variables The following variables are specific to the configuration in which they appear under. Some of these variables appear under multiple configurations. XX Channel Gain Allows the user to manually specify the vertical scale in V/div for XX SUT. XX can be Clock, DQ, DQS, DQSn, ADD/CTRL, or DM. Default is 0 for auto-scale. XX Channel Index Allows the user to manually specify the channel XX SUT. XX can be Clock, DQ, DQS, DQSn, ADD/CTRL, or DM.
QPHY-DDR2 LIMIT SETS DDR2-400 This corresponds to the JEDEC JESD79-2E DDR2 standard specification limits for 400 MT/s. DDR2-533 This corresponds to the JEDEC JESD79-2E DDR2 standard specification limits for 533 MT/s. DDR2-667 This corresponds to the JEDEC JESD79-2E DDR2 standard specification limits for 667 MT/s. DDR2-800 This corresponds to the JEDEC JESD79-2E DDR2 standard specification limits for 800 MT/s.
QPHY-DDR2 Software Option tCH(avg), Average High Pulse Width tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses. tCH(avg) = SUM(tCHi) / (200 x tCK(avg)) where I = 1 to 200 See Figure 20 as follows. tCL(avg), Average Low Pulse Width tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses. tCL(avg) = SUM(tCLi) / (200 x tCK(avg)) where i=1 to 200 See Figure 20 as follows. Figure 20.
tJIT(per), Clock Period Jitter Applicable only to 667 and 800 MHz device only. tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). This test compares the average clock period (over 200 cycles) with each period inside the window. The smallest and largest values must be within limits. tJIT(per) = Min/max of {tCKi - tCK(avg)} where i=1 to 200 Measured on both the rising and the falling edge.
QPHY-DDR2 Software Option 6 ≤ n ≤ 10 for tERR(6-10per) 11 ≤ n ≤ 50 for tERR(11-50per) Measured on both the rising and the falling edge. Eye Diagram Write Burst (Inputs) This is an informational only test that creates the eye diagram of all of the write bursts found in the acquisition. Read Burst (Outputs) This is an informational only test that creates the eye diagram of all of the read bursts found in the acquisition.
or equal to the maximum limit. VIH(dc), minimum DC input logic high Measure the local minimum and maximum values from the first VIH(ac)min crossing point to the time corresponding to VIH(dc)min crossing a 1V/ns slewrate slope to VREF. If multiple pulses are measured, take the lowest, respectively the highest, number as the worst case. The local minimum must be greater than or equal to the minimum limit. The local maximum must be less than or equal to the maximum limit.
QPHY-DDR2 Software Option AC Undershoot, Maximum overshoot area above VDDQ Prerequisite: AC Undershoot maximum peak amplitude, needed to compute area. Maximum undershoot area below VSSQ. Note: The maximum requirements for peak amplitude were reduced from 0.9V to 0.5V. Register vendor data sheets specify the maximum over/undershoot induced in specific RDIMM applications. DRAM vendor data sheets also specify the maximum overshoot/undershoot that their DRAM can tolerate.
not reported in the Jedec JESD79-2E standard. Therefore it is not selected in the standard configurations, but only in the All Tests configuration. Tests Requiring Single Ended Probing of Differential Signal VOX(ac) , AC Differential Output Cross Point Voltage The typical value of VOX(ac) is expected to be about 0.5 x VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ . VOX(ac) indicates the voltage at which differential output signals must cross.
QPHY-DDR2 Software Option tHP, CK half pulse width Prerequisite: needs result of tCL and tCH Clock Tests. tHP refers to the smaller of the actual clock LOW time and the actual clock HIGH time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). tHP is the minimum of the absolute half period of the actual input clock.
Prerequisite: tERR(6-10per), a derating factor is applied to the limit depending on the clock jitter. This is applicable to 667 and 800 MHz device only for both of the following tests.
QPHY-DDR2 Software Option Write Bursts tDQSS, DQS latching rising transitions to associated CK edge CK rising edge at VREF level to DQS rising edge at VREF level, see Figure 26. Figure 26. Burst write operation [JESD79-2E figure 39] tDQSH, DQS Input High Pulse Width DQS High pulse width at VREF level, see Figure 27. Figure 27. Data input (write) timing [JESD79-2E figure 38] tDQSL, DQS Input Low Pulse Width DQS Low pulse width at VREF level, see Figure 27.
tWPRE, Write Preamble Time from when DQS begins to be driven (at the beginning of the preamble) to when it crosses Vref. This is only measured on a write cycle. tWPST, Write Postamble Time from when DQS crosses Vref (at the beginning of the postamble) to when DQS stops being driven (at the end of the postamble). This is only measured on a write cycle. Prerequisite: SLEW of DQ and DQS, a derating factor is applied to the limit depending on the signals slewrate.
QPHY-DDR2 Software Option JESD79-2E Specific Note 8 (page 85 to 94) with tables 43 and 44 explain the limit compensation versus the slewrate of the measured signals. Timing limits are initially specified for input slewrate of 1V/ns for single-ended signals and 2V/ns for differential signal (for DQS and CK). Figure 28. Data input (write) timing [JESD79-2E figure 38] Figure 29.
signal must be monotonic between VIL(dc)max and VIH(dc)min. See Figure 30 as follows. Jedec JESD79-2E Specific Note 8 (page 85 to 94) with table 45 explains the limit compensation versus the slewrate of the measured signals. Timing limits are initially specified for input slewrate of 1V/ns for single-ended signals and 2V/ns for differential signal (for DQS and CK). Figure 30. Single-ended input waveform timing - tDS1 and tDH1 The following tests require probing and address or control signal.
QPHY-DDR2 Software Option tIH(base) - Address and Control Input Hold Time Input waveform timing is referenced from the input signal crossing at the VIL(dc)max level to the differential clock crosspoint at VREF for a rising signal, and from the input signal crossing at the VIH(dc)min level to the differential clock crosspoint at VREF for a falling signal applied to the device under test. See Figure 31 as follows.
