Datasheet

www.tektronix.com/bench 9
Digital Debugging Tips Using a Mixed Signal or Mixed Domain Oscilloscope
At first glance, everything looks fine with the input data
appearing on the output just after the rising clock edge. The
D-Flip-Flop propagation delay is noticeable with the MSO4000
Series’ 60.6 ps high-resolution MagniVu timing acquisition.
The clock positive pulse width is 7.455 ns and the MSO
trigger is configured to find non-conforming clock pulses
less than 6.40 ns. Figure 17 shows the MSO triggered on a
727.3 ps glitch on the clock signal just before the normal clock
pulse. The analog channel is connected to the clock signal to
obtain additional insight into this glitch and the MSO is started
again. Figure 18 shows the MSO triggered on a clock glitch
and the MSO provides the analog insight of what is causing
the glitch. The rising clock edge is non monotonic. Using the
MSO cursors, the clock voltage is determined to be 2 V in
the middle of the glitch and moving the cursor approximately
500 ps to the right, the clock voltage drops to 1.76 V. This
voltage drop caused the logic state to change from logic
high to low for a short time before the clock signal voltage
continued to increase.
The 74F74 specification is 0.8 V
IL
maximum low-level input
voltage and 2 V
IH
minimum high-level input voltage. A clock
signal with slow rise time or non monotonic operation between
V
IL
and V
IH
can cause undefined D-Flip-Flop behavior. Based
on this acquisition, the non monotonic clock edge does not
seem to be causing any problem. The non monotonic clock
edge was documented in the verification report and the next
task is verifying the Q output operation.
The Q output should only change as a result of a change at
the input and the change should only occur at the rising clock
edge plus the D-Flip-Flop propagation delay. The clock has a
fixed period of 20 ns. Therefore, the Q output should not have
any pulses less than 20 ns wide because the Q output should
only change at rising clock edges which are 20 ns apart. The
MSO is configured to trigger on a Q output pulse width less
than 19.2 ns.
Figure 17. MSO capturing a 727.3 ps clock glitch. Figure 18. Clock glitch caused by non monotonic rising clock edge.