Datasheet

Application Note
www.tektronix.com/bench8
Figure 15. 74F74 D-Flip-Flop.
D Input
D Input
Q Output
Q Output
Clock
Clock
74F74
The MSO analog channels are connected to both LVPECL
signals and the MSO is started again looking for small non-
conforming pulses. This time the MSO triggered on a 1.091 ns
glitch and the MSO provides analog insight into both LVPECL
signals as shown in Figure 14. Analog glitches occur at the
same time that the rising edges occur on the other signal.
Most of these analog glitches are below the LVPECL logic
threshold, but some of these glitches cross the logic threshold
and are seen as logic errors such as the glitch on the top
waveform at the left edge of the display.
The MSO provides the significant advantage of capturing both
the signal’s digital and analog characteristics and displaying
them time correlated, providing insight into the signal integrity
of the digital signals. The root cause of these glitches are rising
edge crosstalk between the two LVPECL signals. The LVPECL
rising edge transitions are driven harder and faster than the
falling edges. As a result, the rising edges create significantly
more crosstalk than the falling edges. There is no indication of
falling edge crosstalk in this acquisition.
Non Monotonic Edges and
Setup/Hold Violations
In this example, the TTL 74F74 D-Flip-Flop operation is
verified. The D-Flip-Flop rising clock edge loads the D input
into the Q output as shown in Figure 15. For example, the
Q output is high if the D input is high at the time of the rising
clock edge.
Figure 16 shows the MSO triggered on the rising edge of the
clock which is the bottom waveform. The D-Flip-Flop data
input is the middle waveform and the Q output is the top
waveform. The digital channels have been labeled OUT, DATA
and CLK to make it easy to identify each waveform.
Figure 16. D-Flip-Flop operation looks normal based on one acquisition.
Figure 14. Rising edge crosstalk between two LVPECL signals causing glitches.