Datasheet

Application Note
www.tektronix.com/bench2
Setting Digital Thresholds
A mixed signal oscilloscope’s digital channels view a digital
signal as either a logic high or logic low, just like a digital circuit
views the signal. This means as long as ringing, overshoot and
ground bounce do not cause logic transitions, these analog
characteristics are not of concern to the MSO. Just like a logic
analyzer, an MSO uses a threshold voltage to determine if the
signal is logic high or logic low.
The MSO5000B, MSO4000B and MDO4000B Series provides
per-channel threshold settings that are useful in debugging
circuits with mixed logic families. Figure 1 shows the
MSO4000B measuring five logic signals on one of its digital
probe pods. Three TTL (Transistor-Transistor Logic) signals
and two LVPECL (Low-Voltage Positive Emitter-Coupled Logic)
signals are measured at the same time.
For the MSO2000B and MDO3000 Series, the thresholds
are adjusted per probe pod (a grouping of 8 channels) and
therefore, the TTL signals would be on one pod while the
LVPECL signals would be on the second pod.
Timing and State Acquisitions
There are two major digital acquisition techniques. The first
technique is timing acquisition in which the MSO samples
the digital signal at uniformly spaced times determined by the
MSO’s sample rate. At each sample point, the MSO stores the
signal’s logic state and creates a timing diagram of the signal.
The second digital acquisition technique is state acquisition.
State acquisition defines special times that the digital signal’s
logic state is valid and stable. This is common in synchronous
and clocked digital circuits. A clock signal defines the time
when the signal state is valid. For example, the input signal
stable time is around the rising clock edge for a D-Flip-Flop
with rising edge clocking. The output signal stable time is
around the falling clock edge for a D-Flip-Flop with rising edge
clocking. Since the clock period of a synchronous circuit may
not be fixed, the time between state acquisitions may not be
uniform as it is in a timing acquisition.
Logic analyzers provide both timing and state acquisitions.
A mixed signal oscilloscope’s digital channels acquire signals
similar to how a logic analyzer acquires signals in timing
acquisition mode, as seen in Figure 2. The Tektronix MSO
Series decodes the timing acquisition into a clocked bus
display (Figure 2) and event table (Figure 3) which is similar to
the logic analyzer’s state acquisition display, providing you with
important information during debug.
Figure 1. Mixed logic families (TTL & LVPECL) threshold settings on the same
MSO4000B digital probe pod. The top three channels are TTL signals with a threshold
of 1.40 V and the bottom two channels are LVPECL signals with a threshold of
2.00 V.
Figure 2. Example of a timing acquisition on the MSO Series. Four parallel buses have
been defined and decoded using the device’s clock signal.