Datasheet

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Debugging Serial Buses in Embedded System Designs
In Figure 8, each slave only talks to the master. However,
SPI can be wired with the slave devices daisy-chained, each
performing an operation in turn, and then sending the results
back to the master as shown in Figure 9.
So, as you can see, there is no “standard” for SPI
implementation. In some cases, where communication from
the slave back to the master is not required, the MISO signal
may be left out all together. In other cases there is only one
master and one slave device and the SS signal is tied to
ground. This is commonly referred to as 2-wire SPI.
When an SPI data transfer occurs, an 8-bit data word is
shifted out on MOSI while a different 8-bit data word is being
shifted in on MISO. This can be viewed as a 16-bit circular
shift register. When a transfer occurs, this 16-bit shift register
is shifted 8 positions, thus exchanging the 8-bit data between
the master and slave devices. A pair of registers, clock polarity
(CPOL) and clock phase (CPHA) determine the edges of
the clock on which the data is driven. Each register has two
possible states which allows for four possible combinations, all
of which are incompatible with one another. So a master/slave
pair must use the same parameter values to communicate.
If multiple slaves are used that are fixed in different
configurations, the master will have to reconfigure itself each
time it needs to communicate with a different slave.
SPI
Background
The Serial Peripheral Interface bus (SPI) was originally
developed by Motorola in the late 1980s for their 68000 series
micro-controllers. Due to the simplicity and popularity of the
bus, many other manufacturers have adopted the standard
over the years. It is now found in a broad array of components
commonly used in embedded system design. SPI is primarily
used between micro-controllers and their immediate peripheral
devices. It’s commonly found in cell phones, PDAs, and other
mobile devices to communicate data between the CPU,
keyboard, display, and memory chips.
How It Works
The SPI bus is a master/slave, 4-wire serial communications
bus. The four signals are clock (SCLK), master output/
slave input (MOSI), master input/slave output (MISO), and
slave select (SS). Whenever two devices communicate, one
is referred to as the "master" and the other as the “slave”.
The master drives the serial clock. Data is simultaneously
transmitted and received, making it a full-duplex protocol.
Rather than having unique addresses for each device on the
bus, SPI uses the SS line to specify which device data is being
transferred to or from. As such, each unique device on the bus
needs its own SS signal from the master. If there are 3 slave
devices, there are 3 SS leads from the master, one to each
slave as shown in Figure 8.
Figure 9. Daisy-chained SPI configuration.Figure 8. Common SPI configuration.
SPI Master
Slave #1
SCLK
MISO
MOSI
MISO
SS1
SS1
SS2
SS3
Slave #2
SCLK
MISO
MOSI
Slave #3
SCLK
SCLK
MOSI
SS2
SS3
MISO
MOSI
SPI Master
Slave #1
SCLK SCLK
MOSI
MISO
SS
MOSI
MISO
SS1
SS2
SS3
Slave #2
SCLK
MOSI
MISO
SS
Slave #3
SCLK
MOSI
MISO
SS